Shift register and corresponding driving method, gate driving circuit and display device

A shift register, comprising:

• an input and reset circuit connected to an input terminal, a pull-up node and a reset terminal, and configured to set a potential at the pull-up node to an operating potential when a potential at the input terminal is the operating potential, and set the potential at the pull-up node to a reset potential when a potential at the reset terminal is the operating potential;
• a first output circuit connected to the pull-up node, a first control signal terminal and a first output terminal, and configured to output a first gate driving signal at the first output terminal when the potential at the pull-up node and a potential at the first control signal terminal are the operating potential;
• a second output circuit connected to the pull-up node, a second control signal terminal and a second output terminal, and configured to output a second gate driving signal at the second output terminal when the potential at the pull-up node and a potential at the second control signal terminal are the operating potential;
• a first pull-down circuit connected to a first pull-down node, the pull-up node, the first output terminal and the second output terminal, and configured to set the potentials at the pull-up node, the first output terminal and the second output terminal to the reset potential when a potential at the first pull-down node is the operating potential;
• a second pull-down circuit connected to a second pull-down node, the pull-up node, the first output terminal and the second output terminal, and configured to set the potentials at the pull-up node, the first output terminal and the second output terminal to the reset potential when a potential at the second pull-down node is the operating potential;
• and
• a pull-down node selection circuit connected to a first pull-down node selection signal terminal, a second pull-down node selection signal terminal, the first pull-down node and the second pull-down node, and configured to select one of the first pull-down node and the second pull-down node as an active pull-down node according to the potential at the first pull-down node selection signal terminal and the potential at the second pull-down node selection signal terminal;
• wherein the pull-down node selection circuit comprises:
• a first pull-down selection switching element, a control terminal thereof being connected to the first pull-down node selection signal terminal, and one of a first terminal and a second terminal thereof being connected to the first pull-down node;
• a second pull-down selection switching element, a control terminal thereof being connected to the first pull-down node selection signal terminal, one of a first terminal and a second terminal thereof being connected to the second pull-down node, and the other one of the first terminal and the second terminal thereof being connected to a reference signal terminal;
• a third pull-down selection switching element, a control terminal thereof being connected to the second pull-down node selection signal terminal, one of a first terminal and a second terminal thereof being connected to the second pull-down node, and the other one of the first terminal and the second terminal thereof being connected to the other one of the first terminal and the second terminal of the first pull-down selection switching element;
• and
• a fourth pull-down selection switching element, a control terminal thereof being connected to the second pull-down node selection signal terminal, one of a first terminal and a second terminal thereof being connected to the first pull-down node, and the other one of the first terminal and the second terminal thereof being connected to the reference signal terminal.