Memory proximity disturb management
AssigneeMicron Technology, Inc.
InventorsJeffrey L. McVay, Samuel E. Bradshaw, Justin Eno
Life of this patent
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Abstract
Exemplary methods, apparatuses, and systems include a controller to manage memory proximity disturb. The controller identifies a first memory location in response to an access of a second memory location, the first memory location storing a first value. The controller updates a first disturb value by a first amount, the first disturb value representing a cumulative disturb effect on the first value in the first memory location by accesses to a first plurality of memory locations proximate to the first memory location, the first plurality of memory locations including the second memory location.
Claims20
A method comprising:
- identifying a first memory location in response to an access of a second memory location, the first memory location storing a first value;
- updating a first disturb value by a first amount, the first disturb value representing a cumulative disturb effect on the first value in the first memory location by accesses to a first plurality of memory locations proximate to the first memory location, the first plurality of memory locations including the second memory location;
- and
- in response to a determination that the first disturb value exceeded a disturb threshold:
- reading the first value from the first memory location to obtain a bit-error rate (BER), and
- in response to a determination that the BER is below an error threshold, reducing the first disturb value.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
- identify a first memory location in response to an access of a second memory location, the first memory location storing a first value;
- update a first disturb value by a first amount, the first disturb value representing a cumulative disturb effect on the first value in the first memory location by accesses to a first plurality of memory locations proximate to the first memory location, the first plurality of memory locations including the second memory location;
- and
- in response to a determination that the first disturb value exceeded a disturb threshold, the processing device is further to:
- read the first value from the first memory location to obtain a bit-error rate (BER), and
- in response to a determination that the BER is below an error threshold, reduce the first disturb value.
A system comprising:
- a non-volatile memory component that includes a first memory location and a second memory location;
- and
- a processing device, operatively coupled with the non-volatile memory component, to:
- identify the first memory location in response to an access of the second memory location, the first memory location storing a first value;
- update a first disturb value by a first amount, the first disturb value representing a cumulative disturb effect on the first value in the first memory location by accesses to a first plurality of memory locations proximate to the first memory location, the first plurality of memory locations including the second memory location, and wherein the first amount is based on an orientation of the first memory location relative to the second memory location;
- and
- in response to a determination that the first disturb value exceeded a disturb threshold, the processing device is further to:
- read the first value from the first memory location to obtain a bit-error rate (BER), and
- in response to a determination that the BER is below an error threshold, reduce the first disturb value.
Dependencies are inferred from the claim text.