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US 10,950,316 B2Granted
Apparatus for determining a pass voltage of a read operation
AssigneeMicron Technology, Inc.
InventorsViolante Moschiano, Tecla Ghilardi, Tommaso Vali, Emilio Camerlenghi, William C. Filipiak, Andrea D'Alessandro
Life of this patent
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Abstract
Apparatus having plurality of data lines each selectively connected to a respective string of series-connected memory cells, a plurality of registers each configured to indicate a state of a respective data line, and logic configured to indicate when each data line of the plurality of data lines has a particular state might facilitate determination of a pass voltage of a read operation.
Claims20
An apparatus, comprising:
- an array of memory cells comprising a plurality of strings of series-connected memory cells;
- a plurality of access lines, each access line of the plurality of access lines connected to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- a plurality of data lines, each data line of the plurality of data lines selectively connected to a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- a voltage generation system having an output selectively connected to an access line of the plurality of access lines;
- a plurality of sensing devices, each sensing device of the plurality of sensing devices connected to a respective data line of the plurality of data lines;
- a plurality of registers, each register of the plurality of registers configured to change from a first value to a second value responsive to an output of a respective sensing device of the plurality of sensing devices changing logic levels while the voltage generation system is increasing a voltage level at its output and while the output of the voltage generation system is connected to the access line;
- and
- a logic circuit configured to output a first logic level in response to each register of the plurality of registers having its second value and to output a second logic level, different than its first logic level, in response to any register of the plurality of registers having its first value;
- wherein the voltage generation system is configured to cease increasing the voltage level at its output in response to the logic circuit outputting its first logic level.
6 more elements
A memory, comprising:
- an array of memory cells comprising a plurality of strings of series-connected memory cells;
- a plurality of access lines, each access line of the plurality of access lines connected to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- a plurality of data lines, each data line of the plurality of data lines selectively connected to a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- and
- a controller for access of the array of memory cells, wherein the controller, during a read operation on the plurality of strings of series-connected memory cells, is configured to cause the memory to:
- concurrently increase a respective voltage level applied to each access line of the plurality of access lines during the read operation on the plurality of strings of series-connected memory cells while each data line of the plurality of data lines is connected to its respective string of series-connected memory cells and while each string of series-connected memory cells of the plurality of strings of series-connected memory cells is connected to a common source;
- and
- cease increasing the respective voltage level applied to each access line of the plurality of access lines in response to determining that each data line of the plurality of data lines is connected to the common source through its respective string of series-connected memory cells.
5 more elements
A memory, comprising:
- an array of memory cells comprising a plurality of strings of series-connected memory cells selectively connected to a common source;
- a plurality of access lines, each access line of the plurality of access lines connected to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- a plurality of data lines, each data line of the plurality of data lines selectively connected to a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells;
- a plurality of voltage generation systems;
- and
- a controller for access of the array of memory cells, wherein the controller, during a read operation on the plurality of strings of series-connected memory cells, is configured to cause the memory to:
- for each voltage generation system of the plurality of voltage generation systems, increase a respective voltage level of a respective output of that voltage generation system while the output of that voltage generation system is connected to a respective access line of the plurality of access lines;
- determine whether each string of series-connected memory cells of the plurality of strings of series-connected memory cells has connected its respective data line to the common source while increasing the respective voltage level of the respective output of each voltage generation system of the plurality of voltage generation systems;
- and
- cease increasing the respective voltage level of the respective output of each voltage generation system of the plurality of voltage generation systems in response to determining that each string of series-connected memory cells of the plurality of strings of series-connected memory cells has connected its respective data line to the common source.
7 more elements
Dependencies are inferred from the claim text.