US 10,950,312 B2 · Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line · patentgrep

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Abstract

Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.

Claims20

Dependent claims

A method of operating a memory device, comprising:

comparing input data to data stored in a plurality of memory cells coupled to a data line, wherein the input data comprises a plurality of digits, and wherein each digit of the input data corresponds to a respective pair of memory cells of the plurality of memory cells;
in response to a mismatch between one digit of the input data and the data stored in its respective pair of memory cells, causing a first level of current to flow through its respective pair of memory cells;
in response to a mismatch between another digit of the input data and the data stored in its respective pair of memory cells, causing a second level of current, different than the first level of current, to flow through its respective pair of memory cells;
comparing a representation of a level of current in the data line to a reference;
determining that the input data potentially matches the data stored in the plurality of memory cells in response to the representation of the level of current in the data line being less than the reference;
and
determining that the input data does not match the data stored in the plurality of memory cells in response to the representation of the level of current in the data line being greater than the reference.

4 more elements

A method of operating a memory device, comprising:

comparing input data to data stored in a plurality of memory cells coupled to a data line, wherein the input data comprises a plurality of digits, and wherein each digit of the input data corresponds to a respective pair of memory cells of the plurality of memory cells;
in response to a mismatch between one digit of the input data and the data stored in its respective pair of memory cells, causing a first level of current to flow through its respective pair of memory cells;
in response to a mismatch between another digit of the input data and the data stored in its respective pair of memory cells, causing a second level of current, different than the first level of current, to flow through its respective pair of memory cells;
comparing a representation of a level of current in the data line to a reference;
deeming the input data to match the data stored in the plurality of memory cells in response to the representation of the level of current in the data line being less than the reference;
and
deeming the input data to not match the data stored in the plurality of memory cells in response to the representation of the level of current in the data line being greater than the reference.

4 more elements

A method of operating a memory device, comprising:

comparing input data to stored data, wherein each digit of stored data is stored in a respective pair of memory cells of a respective string of series-connected memory cells of a plurality of strings of series-connected memory cells coupled to a data line, wherein each digit of the input data corresponds to a respective digit of the stored data, and wherein comparing the input data to the stored data comprises comparing a particular digit of the input data to its respective digit of the stored data by applying a pair of voltage levels representative of a value of the particular digit of the input data to control gates of the respective pair of memory cells of its respective string of series-connected memory cells;
in response to a mismatch between one digit of the input data and its respective digit of the stored data, causing a first level of current to flow through its respective string of series-connected memory cells;
in response to a mismatch between another digit of the input data and its respective digit of the stored data, causing a second level of current, different than the first level of current, to flow through its respective string of series-connected memory cells;
comparing a representation of a level of current in the data line to a reference;
deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than or equal to the reference;
and
deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference.

4 more elements

A method of operating a memory device, comprising:

comparing input data to stored data, wherein each digit of stored data is stored in a cells of a plurality of strings of series-connected memory cells coupled to a data line, wherein each digit of the input data corresponds to a respective digit of the comparing a particular digit of the input data to its respective digit of the stored data by applying a pair of voltage levels representative of a value of the particular digit of the input data to control gates of the respective pair of memory cells of its respective string of series-connected memory cells;
causing different levels of current to respectively flow through different strings of series-connected memory cells of the plurality of strings of series-connected memory cells from the data line when different digits of the input data respectively mismatch their respective digits of the stored data;
comparing a representation of a level of current in the data line to a reference;
deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than or equal to the reference;
and
deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference;
wherein causing different levels of current to respectively flow through different strings of series-connected memory cells of the plurality of strings of series-connected memory cells from the data line when different digits of the input data respectively mismatch their respective digits of the stored data comprises causing a first level of current to flow through a first string of series-connected memory cells of the plurality of strings of series-connected memory cells from the data line when its respective digit of the input data has a first significance, and causing a second level of current, less than the first level of current, to flow through a second string of series-connected memory cells of the plurality of strings of series-connected memory cells from the data line when its respective digit of the input data has a second significance less than the first significance.

4 more elements

A method of operating a memory device, comprising:

comparing input data to stored data, wherein each digit of stored data is stored in a respective pair of memory cells of a respective string of series-connected memory cells of a plurality of strings of series-connected memory cells coupled to a data line, wherein each digit of the input data corresponds to a respective digit of the stored data, and wherein comparing the input data to the stored data comprises comparing a particular digit of the input data to its respective digit of the stored data by applying a pair of voltage levels representative of a value of the particular digit of the input data to control gates of the respective pair of memory cells of its respective string of series-connected memory cells;
comparing a representation of a level of current in the data line to a reference;
deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than or equal to the reference;
deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference;
and
storing a particular digit of the stored data in a particular pair of memory cells of the plurality of strings of series-connected memory cells;
wherein storing the particular digit of the stored data in the particular pair of memory cells comprises:
programming a first memory cell of the particular pair of memory cells to a first threshold voltage level when the particular digit of the stored data has a first data value, and programming the first memory cell of the particular pair of memory cells to a second threshold voltage level, different than the first threshold voltage level, when the particular digit of the stored data has a second data value different than the first data value;
and
programming a second memory cell of the particular pair of memory cells to the second threshold voltage level when the particular digit of the stored data has the first data value, and programming the second memory cell of the particular pair of memory cells to the first threshold voltage level when the particular digit of the stored data has the second data value.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/458,384Filed 1 Jul 2019 · continuation
Priority: 17 Apr 2012
Published: US 2019/0074069 A124 Oct 2019
Granted: 16 Mar 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 16/28
Sensing or reading circuits; Data output circuits: using differential sensing or reference cells, e.g. dummy cells
G11C 15/00
Digital stores in which information comprising one or more characteristic parts is
G11C 15/046
Using semiconductor elements: using non-volatile storage elements
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series

Family

Application61/625,286Us provisional application · filed 17 Apr 2012
Application13/864,659Parent of this division · filed 17 Apr 2013
Application14/798,845Parent of this continuation · filed 14 Jul 2015
US 9,105,330 B1Parent of this division · filed 11 Aug 2015
Application15/645,009Parent of this continuation · filed 10 Jul 2017
US 9,728,267 B2Parent of this continuation · filed 8 Aug 2017
Application16/180,154Parent of this continuation · filed 5 Nov 2018
US 10,332,605 B2Parent of this continuation · filed 25 Jun 2019
US 2019/0325971 A1Pre-grant publication · published 24 Oct 2019
US 10,529,430 B2Parent of this continuation
Application14/798,845Parent of this division
US 2015/0318047 A1Published application
US 2017/0309341 A1Published application
US 2019/0074069 A1Published application
US 10,950,312 B2This patent

From the US filing history. Foreign family members aren’t listed.

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