Semiconductor memory column decoder device and method

A method comprising:

• applying an erase voltage to a well of a semiconductor chip;
• raising a potential of a gate of a first transistor via capacitive coupling to the well, wherein the first transistor is positioned in the well;
• raising a potential of a gate of a second transistor via capacitive coupling to the well, wherein the second transistor is positioned in the well;
• turning off an additional transistor responsive to the increased potential of the well when the erase voltage is applied, wherein the additional transistor is configured to be a high voltage transistor;
• and
• applying a precharge voltage to the gate of the first transistor and the gate of the second transistor before applying the erase voltage, wherein the raising the potential of the gates of the first and second transistors comprises raising the potential to a voltage greater than the erase voltage.

A method comprising:

• applying an erase voltage to a well, wherein a first bit line and a second bit line are each coupled to transistors disposed in the well;
• isolating the first bit line and the second bit line from a peripheral circuit with an additional transistor responsive to the applied erase voltage, wherein the additional transistor is configured to be a high voltage transistor;
• raising the potential of the gates of the transistors, wherein the gates of the transistors are capacitively coupled to the well;
• and
• applying a precharge voltage to the gates of the transistors, wherein raising the potential of the gates of the transistors comprises raising the potential of the gates to the precharge voltage plus the erase voltage.

A method comprising:

• applying an erase voltage to a well of a memory device, the memory device comprising:
• a memory string comprising memory cell transistors fabricated in the well;
• a bit line coupled to the memory string;
• a first decoder transistor fabricated in the well and coupled to the bit line;
• a data register buffer outside the well and coupled to the bit line;
• and
• a circuit comprising a high voltage transistor coupled between the data register buffer and the bit line;
• raising a potential of a gate of a first transistor with capacitive coupling between the gate and the well responsive to applying the erase voltage to the well;
• receiving a voltage different than a zero voltage at a gate of the high voltage transistor responsive to applying the erase voltage to the well;
• and
• turning off the high voltage transistor responsive to the received voltage at the gate of the high voltage transistor.