Semiconductor memory device
AssigneeKioxia Corporation
InventorNaoya Tokiwa
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes memory cells, a first circuit that includes a first latch group including first and second data latch circuits and a second latch group including third and fourth data latch circuits, and a control circuit configured to control a write operation during which first and second data to be written into the memory cells are stored in the first and second data latch circuits, respectively, wherein the first and second data are also stored in the third and fourth data latch circuits, respectively, while the first and second data stored in the first and second data latch circuits, respectively, are being written in the memory cells.
Claims18
A semiconductor memory device comprising:
- memory cells;
- a first circuit that includes a first latch group including first and second data latch circuits and a second latch group including third and fourth data latch circuits;
- and
- a control circuit configured to control a write operation during which first and second data to be written into the memory cells are stored in the first and second data latch circuits, respectively, wherein the first and second data are also stored in the third and fourth data latch circuits, respectively, while the first and second data stored in the first and second data latch circuits, respectively, are being written in the memory cells.
A semiconductor memory device comprising:
- memory cells;
- a first circuit that includes first, second, third, and fourth data latch circuits;
- and
- a control circuit configured to:
- store first and second data in the first and second data latch circuits, respectively, when performing a write operation on the memory cells,
- store data read from the memory cells in the third data latch circuit in response to a first command that is received during the write operation, and
- store data read from the memory cells in the fourth data latch circuit in response to a second command that is received during the write operation.
A semiconductor memory device comprising:
- first memory cells connected to a first word line;
- second memory cells connected to a second word line;
- a first circuit that includes a sense amplifier and a data line connected to the sense amplifier, first, second, and third data latch circuits connected in series, and fourth, fifth, and sixth data latch circuits connected in series, wherein the data line is connected to the first and fourth data latch circuits so that data can be transmitted between the data line and the first and fourth data latch circuits and to the third and sixth data latch circuits so that data can be received therefrom;
- and
- a control circuit configured to perform a write operation that includes a foggy program operation and a fine program operation, wherein
- during the foggy program operation of the first memory cells, first and second data to be written into the first memory cells are stored in the first and fourth data latch circuits, respectively, and in the second and fifth data latch circuits, respectively, and third and fourth data to be written in to the second memory cells are stored in the third and sixth data latch circuits, respectively.
Dependencies are inferred from the claim text.