Memory device having improved program and erase operations and operating method of the memory device

A method for operating a memory device, the method comprising:

• floating gates of some source select transistors among a plurality of source select transistors included in an unselected memory block among a plurality of memory blocks each including the plurality of source select transistors, a plurality of memory cells, and a drain select transistor, which are coupled in series between a source line and a bit line;
• applying a precharge voltage to the source line;
• and
• applying a program voltage and a pass voltage to word lines coupled to a selected memory block among the plurality of memory blocks.

A method for operating a memory device, the method comprising:

• providing a memory block including a plurality of source select transistors, a plurality of memory cells, and a drain select transistor, which are coupled in series between a source line and a bit line;
• applying a first erase voltage to the source line;
• floating some source select transistors among the plurality of source select transistors;
• increasing the first erase voltage to a second erase voltage and applying the second erase voltage to the source line;
• and
• floating other source select transistors among the plurality of source select transistors.