RRAM current limiting circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Cheng Chou, Pei-Ling Tseng, Zheng-Jun Lin
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Abstract
A circuit includes a bias voltage generator and a current limiter. The bias voltage generator is configured to receive a first reference voltage and output a bias voltage responsive to a first current and the first reference voltage. The current limiter is configured to receive a second current at an input terminal, a second reference voltage, and the bias voltage, and, responsive to the second reference voltage and a voltage level of the input terminal, limit the second current to a current limit level, the voltage level of the input terminal being based on the bias voltage.
Claims20
A circuit comprising:
- a bias voltage generator configured to receive a first reference voltage, and output a bias voltage responsive to a first current and the first reference voltage;
- and
- a current limiter comprising an input terminal and a first current path in parallel with a second current path, wherein
- the first and second current paths are configured to conduct a second current received at the input terminal,
- each of a first transistor in the first current path and a second transistor in the second current path comprises a gate configured to receive the bias voltage,
- the current limiter is configured to, responsive to a second reference voltage and a voltage level of the input terminal, limit the second current to a current limit level, and
- the voltage level of the input terminal is based on the bias voltage.
A resistive random-access memory (RRAM) circuit comprising:
- an RRAM device configured to output a cell current responsive to a bit line voltage;
- a bias voltage generator configured to receive a first current and a reference voltage, and output a bias voltage responsive to the first current and the reference voltage;
- and
- a current limiter comprising a first transistor and a second transistor, each of the first and second transistors comprising a gate configured to receive the bias voltage,
- wherein
- the current limiter is configured to further receive the cell current and the reference voltage, and, responsive to the cell current, the reference voltage, and the bias voltage, limit the cell current to a current limit level, and
- the bias voltage generator is configured to generate the bias voltage having a bias voltage level corresponding to a source/drain terminal of each of the first and second transistors having a voltage level of the reference voltage.
A resistive random-access memory (RRAM) circuit comprising:
- an RRAM device configured to output a cell current responsive to a bit line voltage;
- a first transistor comprising a drain terminal configured to receive a first current;
- an amplifier configured to generate a bias voltage by maintaining a first drain voltage at the drain terminal at a first reference voltage level;
- a second transistor coupled between the RRAM device and a first switching device, and comprising a gate configured to receive the bias voltage;
- a third transistor coupled between the RRAM device and a second switching device, and comprising a gate configured to receive the bias voltage;
- and
- a comparator coupled to a source/drain terminal of each of the second and third transistors, and configured to switch off the second switching device responsive to a second drain voltage at the source/drain terminals exceeding a second reference voltage level.
Dependencies are inferred from the claim text.