Mixed threshold voltage memory array

A static random access memory (SRAM) device, comprising:

• a first memory array including a plurality of memory cells connected to a bit line, each of the plurality of memory cells having a first threshold voltage;
• a second memory array including a plurality of memory cells connected to the bit line, each of the plurality of memory cells having a second threshold voltage;
• a peripheral input-output (I/O) circuit connected to the bit line;
• a column of write current tracking cells, each tracking cell disposed within a row of the first memory array and the second memory array;
• wherein the first memory array is between the peripheral input-output circuit and the second memory array.

A method of forming a static random access memory (SRAM) device, comprising:

• providing a first memory array including a plurality of memory cells, each memory cell including a first pass gate transistor with a first threshold voltage;
• providing a second memory array including a plurality of memory cells, each memory cell including a second pass gate transistor with a second threshold voltage;
• coupling the first pass gate transistor to a bit line and coupling the second pass gate transistor to the bit line;
• coupling a peripheral input-output (I/O) circuit to the bit line, wherein the first memory array is between the peripheral input-output circuit and the second memory array;
• and
• providing a column of write current tracking cells, the write current tracking cells including a first tracking cell disposed within a row of the first memory array and having a first tracking threshold voltage, and a second tracking cell disposed within a row of the second memory array and having a second tracking threshold voltage.