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US 10,950,295 B2Granted
Memory cell array having three-dimensional structure
AssigneeToshiba Memory Corporation
InventorsChika Tanaka, Keiji Ikeda
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a semiconductor memory includes a first bit line; a second bit line; a source line; a first memory cell electrically connected between the first bit line and the source line and including a first transistor and a first capacitor; a second memory cell electrically connected between the second bit line and the source line and including a second transistor and a second capacitor; a third transistor electrically connected to the source line; and a sense amplifier circuit including a first node electrically connected to the first bit line and a second node electrically connected to the second bit line.
Claims16
A semiconductor memory comprising:
- a first bit line;
- a second bit line;
- a source line;
- a first memory cell electrically connected between the first bit line and the source line and including a first transistor and a first capacitor;
- a second memory cell electrically connected between the second bit line and the source line and including a second transistor and a second capacitor;
- a third transistor electrically connected to the source line;
- and
- a sense amplifier circuit including:
- a first node electrically connected to the first bit line and a second node electrically connected to the second bit line;
- a first sense unit including a first input terminal electrically connected to the first node via a first transfer gate and a second input terminal electrically connected to the second node via a second transfer gate;
- a second sense unit including a third input terminal electrically connected to the first node and a fourth input terminal electrically connected to the second node;
- a first capacitor including a first terminal electrically connected to the first input terminal of the first sense unit and a second terminal electrically connected to the fourth input terminal of the second sense unit;
- and
- a second capacitor including a third terminal electrically connected to the second input terminal of the first sense unit and a fourth terminal electrically connected to the third input terminal of the second sense unit.
11 more elements
A semiconductor memory comprising:
- a first bit line provided above a semiconductor substrate in a first direction perpendicular to a first surface of the semiconductor substrate;
- a second bit line provided above the first bit line in the first direction;
- a source line provided between the first bit line and the second bit line;
- a first memory cell including a first transistor provided between the first bit line and the source line and a first capacitor provided between the first transistor and the source line;
- a second memory cell including a second transistor provided between the second bit line and the source line and a second capacitor provided between the second transistor and the source line;
- a first word line provided between the first bit line and the source line and connected to a gate of the first transistor;
- a second word line provided between the second bit line and the source line and connected to a gate of the second transistor;
- a sense amplifier circuit provided on the semiconductor substrate;
- and
- a third transistor provided between the semiconductor substrate and the source line,
- wherein the sense amplifier circuit includes:
- a first node electrically connected to the first bit line and a second node electrically connected to the second bit line,
- a first sense unit including a first input terminal electrically connected to the first node via a first transfer gate and a second input terminal electrically connected to the second node via a second transfer gate;
- a second sense unit including a third input terminal electrically connected to the first node and a fourth input terminal electrically connected to the second node;
- a first capacitor including a first terminal electrically connected to the first input terminal of the first sense unit and a second terminal electrically connected to the fourth input terminal of the second sense unit;
- and
- a second capacitor including a third terminal electrically connected to the second input terminal of the first sense unit and a fourth terminal electrically connected to the third input terminal of the second sense unit.
14 more elements
Dependencies are inferred from the claim text.