Signal processing circuit, distributed memory, ROM, and DAC which signal processing circuit is embedded

A distributed memory comprising:

• a signal processing circuit including
• one serial port to which an N-bit word is input,
• 2N first output ports corresponding uniquely to 2N bit combinations and spatially separated from one another, and
• a recognition circuit including determination stages corresponding to the respective bits of the input word input through the serial port, wherein the recognition circuit further includes a serial-parallel converter configured to generate and output, for each bit of the input word, an optical pulse being a control signal indicative of a state of the bit, the determination stages each including a determination unit configured to output, in a case where an electric pulse is input to the determination unit to activate the determination unit, the electric pulse to one of two second output ports according to the optical pulse indicative of a state of a corresponding bit of the input word, the two second output ports of the determination unit being connected to different determination units corresponding to an adjacent lower bit, the second output ports of the determination units corresponding to a lowest bit of the input word being connected to the first output ports;
• 2N RAM chips corresponding uniquely to the 2N first output ports of the signal processing circuit and made active only in a case where an electric pulse is output from the first output port;
• wherein an input address signal includes a first portion of N bits and a second portion of M bits, the signal processing circuit recognizes the first portion and the 2N RAM chips recognize the second portion.

A ROM comprising:

• a first decoder and a second decoder each including a signal processing circuit and configured to decode a memory address from an input address signal, the signal processing circuit including
• one serial port to which an N-bit word is input,
• 2N first output ports corresponding uniquely to 2N bit combinations and spatially separated from one another, and
• a recognition circuit including determination stages corresponding to the respective bits of the input word input through the serial port, wherein the recognition circuit further includes a serial-parallel converter configured to generate and output, for each bit of the input word, an optical pulse being a control signal indicative of a state of the bit, the determination stages each including a determination unit configured to output, in a case where an electric pulse is input to the determination unit to activate the determination unit, the electric pulse to one of two second output ports according to the optical pulse indicative of a state of a corresponding bit of the input word, two second output ports of the determination unit being connected to different determination units corresponding to an adjacent lower bit, the second output ports of the determination units corresponding to a lowest bit of the input word being connected to the first output ports;
• a memory cell array connected to the first and second decoders and including a plurality of two-dimensionally arranged memory cells corresponding to the memory address decoded;
• and
• an output sensor connected to each of the memory cells of the memory cell array and configured to output data from a memory cell designated by the first and second decoder.

A DAC comprising:

• a signal processing circuit including
• one serial port to which an N-bit word is input,
• 2N first output ports corresponding uniquely to 2N bit combinations and spatially separated from one another, and
• a recognition circuit including determination stages corresponding to the respective bits of the input word input through the serial port, wherein the recognition circuit further includes a serial-parallel converter configured to generate and output, for each bit of the input word, an optical pulse being a control signal indicative of a state of the bit, the determination stages each including a determination unit configured to output, in a case where an electric pulse is input to the determination unit to activate the determination unit, the electric pulse to one of two second output ports according to the optical pulse indicative of a state of a corresponding bit of the input word, the two second output ports of the determination unit being connected to different determination units corresponding to an adjacent lower bit, the second output ports of the determination units corresponding to a lowest bit of the input word being connected to the first output ports;
• and
• an analog output voltage generator including 2N input ports corresponding uniquely to the 2N first output ports of the signal processing circuit, the 2N input ports controlling generation of voltages at 2N output voltage levels and causing the analog output voltage generator to generate a voltage at a predetermined voltage level only in a case where an electric pulse is output from the first output ports.