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US 10,950,291 B1Granted
Apparatuses and methods to perform duty cycle adjustment with back-bias voltage
AssigneeMicron Technology, Inc.
InventorsMichael V. Ho, Myung Ho Bae
Life of this patent
Estimating the term…
Abstract
An exemplary semiconductor device includes a clock generator circuit configured to generate a clock signal, and a duty cycle adjustment circuit configured to receive the clock signal. The duty cycle adjustment circuit includes an adjuster circuit configured to receive a back-bias voltage and to adjust a duty cycle of the clock signal based on the back-bias voltage to provide an output clock signal.
Claims21
An apparatus comprising;
- a clock generator circuit configured to generate a clock signal;
- and
- a duty cycle adjustment circuit configured to receive the clock signal, wherein the duty cycle adjustment circuit comprises an adjuster circuit configured to receive a back-bias voltage and to adjust a duty cycle of the clock signal based on the back-bias voltage to provide an output clock signal, wherein the adjuster circuit includes a first step generator configured to receive the back-bias voltage, and wherein the first step generator is selectively enabled by a signal different from the clock signal to adjust the duty cycle of the clock signal by a first amount based on the back-bias voltage.
An apparatus, comprising:
- a clock generator circuit configured to generate a clock signal;
- and
- a duty cycle adjustment circuit configured to receive the clock signal, wherein the duty cycle adjustment circuit comprises an adjuster circuit configured to receive a back-bias voltage and to adjust a duty cycle of the clock signal based on the back-bias voltage to provide an output clock signal, wherein the duty cycle adjustment circuit further includes a decoder circuit configured to decode a mode register setting to provide a control signal to the adjuster circuit, wherein the adjuster circuit is further configured to adjust the duty cycle of the clock signal based on the control signal.
A memory comprising:
- a duty cycle adjustment circuit comprising:
- an adjuster circuit configured to receive a back-bias voltage, a clock signal, and a control signal, wherein the adjustor circuit is configured to adjust a duty cycle of the clock signal based on the back-bias voltage and the control signal to provide an output clock signal;
- and
- a decoder circuit configured to receive a mode register setting and to decode the mode register setting to provide the control signal to the adjustor circuit, wherein an amount of the adjustment of the duty cycle of the clock signal is based on a value of the control signal.
1 more element
A method comprising:
- receiving, at a duty cycle adjustment circuit, a mode register setting, a clock signal, and a back-bias voltage, wherein the back-bias voltage includes a supply voltage adjusted by a bias voltage amount;
- decoding the mode register setting to determine a duty cycle adjustment amount;
- adjusting a duty cycle of the clock signal based on the determined duty cycle adjustment amount and the back-bias voltage to provide an output clock signal.
Dependencies are inferred from the claim text.