Memory device and operating method thereof that reduce off current to reduce errors in reading and writing data which have plurality of memory cell blocks and a source voltage generator

A memory device, comprising:

• a plurality of memory cell blocks, each of the memory cell blocks having at least two memory cells;
• and
• a source voltage generator, the source voltage generator coupled to the plurality of memory cell blocks, configured to:
• cause a source voltage of the memory cell block to be a first voltage according to that a memory cell in each of the memory cell blocks is in a selected state,
• cause the source voltage of the memory cell block to be a second voltage according to that all memory cells in each of the memory cell blocks are in an unselected state,
• wherein an absolute value of the first voltage is less than an absolute value of the second voltage,
• wherein the source voltage generator comprises:
• a logic operation circuit, performing a logical operation on the plurality of memory cell blocks to generate the source voltage,
• wherein the logic operation circuit comprises:
• a plurality of logic gates respectively coupled to the plurality of memory cell blocks, the plurality of logic gates respectively receiving selection signals of the at least two memory cells in the plurality of memory cell blocks and outputting a plurality of control signals separately;
• and
• a plurality of multiplexers respectively coupled to the plurality of logic gates, wherein the plurality of multiplexers selectively output the first voltage or the second voltage to source terminals of the at least two memory cells in the plurality of memory cell blocks according to the plurality of control signals respectively.