Semiconductor device
AssigneeMicron Technology, Inc.
InventorsYutaka Ito, Yuan He
Life of this patent
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Abstract
A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a corresponding one of the plurality of memory cells MC; and a control circuit that intermittently monitors accesses to the plurality of word lines WL, stores/erases some captured row-addresses in a first number of registers, and detects, by comparison with stored addresses, in response to a first number of accesses to one of the word lines WL in a first period of time. According to the present invention, access histories can be precisely analyzed by a small-scale circuit configuration, and measures against, for example, the Row Hammer problem, etc. can be taken.
Claims17
An apparatus comprising:
- a row decoder configured to receive a refresh address and to selectively perform a row-copy operation, wherein during the row-copy operation data in a first word line corresponding to the refresh address is copied to a second word line in a same section of a memory as the first address;
- and
- a refresh address control circuit configured to receive a row address, store the received row address as one of a plurality of stored address responsive to a sampling signal, and compare the received row address to the plurality of stored addresses, wherein if there is a match, the refresh address control circuit is configured to provide the refresh address based on the received row address.
A method comprising:
- identifying a row hammer address corresponding to a first word line of a memory, wherein the identifying the row hammer address comprises receiving a row address, storing the received row address as one of a plurality of stored addresses responsive to a sampling signal, and comparing the received row address to the plurality of stored addresses, wherein if there is a match between the received row address and one of the plurality of stored addresses, the received address is identified as the row hammer address;
- determining if a second word line in a same section of the memory as the first word line has a vacant region;
- and
- copying data from a region of the first word line to the vacant region of the second word line.
An apparatus comprising:
- a refresh address control circuit configured to provide a refresh address based on accesses to a plurality of word lines, wherein the refresh address control circuit comprises:
- a sampling signal generator configured to provide a sampling signal;
- a shift register configured to store a plurality of row addresses associated with the accesses to the plurality of word lines responsive to the sampling signal;
- and
- a plurality of comparator circuits configured to compare a received row address to the plurality of row addresses in the shift register, wherein the refresh address is based on received row address responsive to at least one of the plurality of comparator circuits determining a match;
- and
- a row decoder configured to receive the refresh address and selectively perform a row copy operation, wherein the row-copy operation involves copying data from a first word line based on the refresh address to a second word line which shares a sense amplifier and a bit line with the first word line.
Dependencies are inferred from the claim text.