Periphery fill and localized capacitance
AssigneeMicron Technology, Inc.
InventorsChristopher John Kawamura, Scott James Derner
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for periphery fill and localized capacitance are described. A memory array may be fabricated with certain containers connected to provide capacitance rather than to operate as memory cells. For example, a memory cell having one or two transistors, or other switching components, and one capacitor, such as a ferroelectric or dielectric capacitor, may be electrically isolated from one or more containers sharing a common access line, and the isolated containers may be used as capacitors. The capacitors may be used for filtering in some examples. Or the capacitance may be used to boost or regulate voltage in, for example, support circuitry.
Claims19
A apparatus, comprising:
- an array of memory cells, wherein one or more memory cells of the array are coupled with a first segment of a first access line;
- a capacitor coupled with a second segment of the first access line, wherein the second segment of the first access line is isolated from the first segment of the first access line;
- and
- circuitry coupled to the array of memory cells and the capacitor, wherein the array of memory cells and the capacitor overlie at least a portion of the circuitry.
An apparatus, comprising:
- a memory cell that comprises a memory element coupled with a second access line segment and coupled with a selector device that is coupled with a first access line segment;
- and
- a capacitor formed in a container type common to the memory cell, wherein the capacitor is coupled with a third access line segment and a fourth access line segment, wherein the first access line segment and the second access line segment are electrically isolated from the third access line segment and the fourth access line segment, and wherein the first access line segment and the third access line segment are formed from a same access line.
An apparatus, comprising:
- a memory cell that comprises a memory element coupled with a second access line segment and coupled with a selector device that is coupled with a first access line segment;
- and
- a capacitor formed in a container type common to the memory cell, wherein the capacitor is coupled with a third access line segment and a fourth access line segment, wherein the first access line segment and the second access line segment are electrically isolated from the third access line segment and the fourth access line segment, wherein the memory element is coupled with the first access line segment via a first transistor and the second access line segment via a second transistor and wherein the capacitor is coupled with the third access line segment via a third transistor and the fourth access line segment via a fourth transistor.
An apparatus, comprising:
- a memory cell that comprises a memory element coupled with a second access line segment and coupled with a selector device that is coupled with a first access line segment;
- circuitry coupled with the memory cell;
- a capacitor formed in a container type common to the memory cell and coupled with a third access line segment and a fourth access line segment, wherein the first access line segment and the second access line segment are electrically isolated from the third access line segment and the fourth access line segment, and wherein the first access line segment and the third access line segment are formed from a same access line;
- and
- a memory controller coupled with the memory cell, the circuitry, and the capacitor, the memory controller operable to cause the apparatus to:
- perform an access operation on the memory cell;
- and
- couple the capacitor with a node in the circuitry while performing the access operation on the memory cell.
Dependencies are inferred from the claim text.