Semiconductor devices
AssigneeSK hynix Inc.
InventorWoongrae Kim
Life of this patent
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Abstract
A semiconductor device includes a latch signal generation circuit and a training result signal generation circuit. The latch signal generation circuit latches a first internal control signal and a second internal control signal to generate a first latch signal and a second latch signal. The first internal control signal is generated based on a first internal clock signal and a control signal, and the second internal control signal is generated. The training result signal generation circuit is synchronized with a first alignment pulse and a second alignment pulse generated based on the first latch signal and the latch signal, thereby generating a training result signal from the first and second latch signals.
Claims22
A semiconductor device comprising:
- a latch signal generation circuit configured to latch a first internal control signal and a second internal control signal in synchronization with a latch clock signal to generate a first latch signal and a second latch signal, wherein the first internal control signal is generated based on a first internal clock signal and a control signal, and wherein the second internal control signal is generated based on a second internal clock signal and the control signal;
- and
- a training result signal generation circuit configured to be synchronized with a first alignment pulse and a second alignment pulse generated based on the first latch signal and the second latch signal to generate a training result signal from the first and second latch signals.
A semiconductor device comprising:
- a latch signal generation circuit configured to latch a first internal control signal and a second internal control signal in synchronization with a latch clock signal to generate a first latch signal and a second latch signal, wherein the first and second internal control signals are generated based on a control signal, a first internal clock signal, and a second internal clock signal;
- an alignment pulse generation circuit configured to generate a first alignment pulse during a first period when the first latch signal is set to have a predetermined logic level and configured to generate a second alignment pulse during a second period when the first latch signal is set to have the predetermined logic level;
- and
- a training result signal generation circuit configured to generate a training result signal having a level transition occurring when the control signal is toggled in synchronization with the first and second internal clock signals.
A semiconductor device comprising:
- a latch signal generation circuit configured to latch a first internal control signal and a second internal control signal in synchronization with a latch clock signal to generate a first latch signal and a second latch signal, wherein the first internal control signal is generated based on a first internal clock signal and a control signal, and wherein the second internal control signal is generated based on a second internal clock signal and the control signal;
- and
- a training result signal generation circuit configured to generate a training result signal from the first and second latch signals, the training result signal indicating when the control signal is toggling in synchronization with the first internal clock signal and the second internal clock signal during a test period.
Dependencies are inferred from the claim text.