US 10,950,282 B2 · Methods for on-die memory termination and memory devices and systems employing the same

Abstract

Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

Claims16

Dependent claims

A method of operating a memory system, comprising:

receiving a first command instructing a memory device of the memory system to enter an on-die termination mode;
in response to the first command, placing the memory device in the on-die termination mode;
and
maintaining the memory device in the on-die termination mode for longer than a duration of a data communication of the memory system.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

16/540,011Filed 13 Aug 2019 · continuation

Priority

22 Nov 2017

Published

US 2019/0156871 A15 Dec 2019

Granted

16 Mar 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
G06F 13/4086
Electrical coupling: bus impedance matching, e.g. termination
G11C 7/1045
Read-write modes for single port memories, i.e. having either a random port or a serial port: read-write mode select circuits
G11C 7/1057
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output…

Family

Application62/590,096Us provisional application · filed 22 Nov 2017

Application16/047,954Parent of this continuation · filed 27 Jul 2018

US 2019/0371379 A1Pre-grant publication · published 5 Dec 2019

US 10,424,356 B2Parent of this continuation

US 2019/0156871 A1Published application

US 10,950,282 B2This patent

From the US filing history. Foreign family members aren’t listed.

Methods for on-die memory termination and memory devices and systems employing the same

Life of this patent

Methods for on-die memory termination and memory devices and systems employing the same

Life of this patent

Abstract

Claims16