Electronic device comprising storage devices transmitting reference clock via cascade coupling structure
AssigneeSamsung Electronics Co., Ltd.
InventorsYongwoo Jeong, Hwaseok Oh, JinHyeok Choi
Life of this patent
Estimating the term…
Abstract
Disclosed is an electronic device which includes an application processor configured to generate a reference clock, a first storage device configured to receive the reference clock from the application processor through a clock input port, to output the reference clock to a clock output port, and to communicate with the application processor by using the reference clock, and a second storage device configured to receive the reference clock from the clock output port and use the reference clock for communication with the first storage device.
Claims19
An electronic device comprising:
- a first storage device configured to receive a first reference clock signal through a clock input port, and output a second reference clock signal to a clock output port;
- and
- a second storage device configured to receive the second reference clock signal output from the clock output port, and use the second reference clock signal to communicate with the first storage device, the second reference clock signal having at least one clock signal parameter different than the first reference clock signal, and
- wherein a frequency of the first reference clock signal is different from a frequency of the second reference clock signal.
An embedded storage device comprising:
- a nonvolatile memory;
- a controller configured to control the nonvolatile memory;
- a clock input port configured to receive a first reference clock signal and transmit the first reference clock signal to the controller;
- and
- a clock output port configured to output a second reference clock signal provided from the controller,
- wherein the controller is configured to bypass the first reference clock signal provided from the clock input port to the clock output port, or transmit the second reference clock signal to the clock output port after tuning the first reference clock signal.
An electronic device comprising:
- a first storage device configured to receive a first reference clock signal through a first clock signal input port, and output a second reference clock signal to a first clock output port, the second reference clock signal having at least one clock signal parameter different than the first reference clock signal, wherein the first storage device includes,
- a first controller configured to receive the first reference clock signal and first data from the first clock input port and output the second reference clock signal to the first clock output port, and
- a first nonvolatile memory configured to store the first data from the first controller;
- and
- a second storage device configured to receive the second reference clock signal output from the first clock output port, wherein the second storage device includes,
- a second clock input port configured to receive the second reference clock signal, and
- a second controller configured to receive the second reference clock signal from the second clock input port and second data;
- and
- a second nonvolatile memory configured to store the second data from the second controller, and wherein
- the first storage device is further configured to communicate with an operation processor supplying the first data and the first reference clock signal by using the first reference clock signal, and
- the second storage device is further configured to communicate with the first storage device by using the second reference clock signal.
Dependencies are inferred from the claim text.