Bit line sense amplifier circuit capable of reducing offset voltage

A bit line sense amplifier (BLSA) circuit comprising:

• a first inverter having an input terminal coupled to a first sensing node and an output terminal coupled to a second inner bit line;
• a second inverter having an input terminal coupled to a second sensing node and an output terminal coupled to a first inner bit line;
• a first capacitor coupled to and disposed between a first bit line and the first sensing node;
• a second capacitor coupled to and disposed between a second bit line and the second sensing node;
• a first offset canceling switch suitable for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation;
• a second offset canceling switch suitable for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation;
• a first isolation switch suitable for electrically coupling the first bit line with the first inner bit line;
• and
• a second isolation switch suitable for electrically coupling the second bit line with the second inner bit line,
• wherein the BLSA circuit sequentially performs a precharge operation, the offset canceling operation, a charge sharing operation, and an amplification operation, and
• wherein during the charge sharing operation, the first and second inverters are activated, and charge sharing is performed between a selected memory cell and one of the first and second bit lines to which the selected memory cell is coupled, when the first and second offset canceling switches and the first and second isolation switches are being turned off.

A bit line sense amplifier (BLSA) circuit comprising:

• a first inverter having an input terminal coupled to a first sensing node and an output terminal coupled to a second inner bit line;
• a second inverter having an input terminal coupled to a second sensing node and an output terminal coupled to a first inner bit line;
• a first capacitor coupled to and disposed between a first bit line and the first sensing node;
• a second capacitor coupled to and disposed between a second bit line and the second sensing node;
• a first offset canceling switch suitable for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation;
• a second offset canceling switch suitable for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation;
• a first isolation switch suitable for electrically coupling the first bit line with the first inner bit line;
• and
• a second isolation switch suitable for electrically coupling the second bit line with the second inner bit line,
• wherein the BLSA circuit sequentially performs a precharge operation, the offset canceling operation, a charge sharing operation, and an amplification operation, and
• wherein during the amplification operation, the first and second inverters are activated, the first and second isolation switches are turned on, and the first and second offset canceling switches are turned off.

A bit line sense amplifier (BLSA) circuit comprising:

• a first inverter having an input terminal coupled to a first sensing node and an output terminal coupled to a second inner bit line;
• a second inverter having an input terminal coupled to a second sensing node and an output terminal coupled to a first inner bit line;
• a first capacitor coupled to and disposed between a first bit line and the first sensing node;
• a second capacitor coupled to and disposed between a second bit line and the second sensing node;
• a first offset canceling switch suitable for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation;
• a second offset canceling switch suitable for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation;
• a first isolation switch suitable for electrically coupling the first bit line with the first inner bit line;
• and
• a second isolation switch suitable for electrically coupling the second bit line with the second inner bit line,
• wherein the BLSA circuit sequentially performs a precharge operation, the offset canceling operation, a charge sharing operation, a pre-amplification operation, and an amplification operation.