Nonvolatile memory device including memory element in equal cross-sectional area of word lines and bit lines

A nonvolatile memory device comprising:

• a first word line extending in a first direction;
• a second word line extending in the first direction;
• a first bit line extending in a second direction intersecting the first direction;
• a second bit line extending in the second direction;
• memory cells connected between the first word line and the first bit line, between the first word line and the second bit line, between the second word line and the first bit line, and between the second word line and the second bit line, respectively, and each including a resistance change memory element;
• a global word line extending in the second direction;
• a global bit line extending in the first direction;
• a first word line select circuit connected between the first word line and the global word line;
• a second word line select circuit connected between the second word line and the global word line;
• a first bit line select circuit connected between the first bit line and the global bit line;
• a second bit line select circuit connected between the second bit line and the global bit line;
• a word line driver connected to the global word line, and supplying a first signal to the first word line selected by the first word line select circuit and to the second word line selected by the second word line select circuit;
• and
• a bit line driver connected to the global bit line, and supplying a second signal to the first bit line selected by the first bit line select circuit and to the second bit line selected by the second bit line select circuit,
• wherein the first word line and the second word line both have a first line width and a first line thickness,
• the first bit line and the second bit line both have a second line width and a second line thickness,
• the global word line includes a first global word line portion having the second line width and the second line thickness,
• the global bit line includes a first global bit line portion having the first line width and the first line thickness,
• the first global word line portion has a first end portion to which a signal from the word line driver is input,
• the first global bit line portion has a second end portion to which a signal from the bit line driver is input, and
• the first word line is nearer than the second word line with respect to the first end portion, the second word line is nearer than the first word line with respect to the second end portion, the first bit line is nearer than the second bit line with respect to the first end portion, and the second bit line is nearer than the first bit line with respect to the second end portion.