Combination circuitry for multiple embedded display transmission protocols

A physical layer system comprising:

• a Mobile Industry Processor Interface (MIPI) display serial interface (DSI) logic element configured to receive data compliant with a MIPI DSI protocol and output a differential pair signal to a parallel input/serial output (PISO) circuit element;
• a CPHY logical element comprising:
• a mapper circuit to map a 16 bit input to a 21 bit output, mapper circuit comprising three 7 bit outputs;
• for each 7 bit output, a serializer circuit element;
• an encoder downstream of the serializer circuit element;
• and
• a deserializer circuit element to output a trio to a multiplexer circuit element;
• wherein:
• the multiplexer circuit element is downstream of the PISO and is coupled to an output of the PISO, the multiplexer configured to output one of the MIPI DSI or the CPHY data to an display driver.

A method comprising:

• receiving a display signal at a display controller;
• determining that the signal is one of an eDisplayPort (eDP)-compliant signal, a display serial interface (DSI)-compliant signal, or a CPHY-compliant signal;
• for a eDP-compliant signal or a DSI-compliant signal:
• forming a differential pair;
• serializing the differential pair;
• and
• directing the differential pair to a multiplexer;
• for a CPHY-compliant signal:
• forming a trio of data symbols;
• encoding the trio of data symbols;
• and
• directing the trio of data symbols to the multiplexer;
• and
• outputting from the multiplexer a serialized set of display data symbols to one or more display drivers;
• the method further comprising:
• receiving at the multiplexer eDP or DSI differential pairs as an output from a parallel input to serial output (PISO) circuit element or a trio of CPHY symbols;
• and
• outputting to a display driver one of the eDP or DSI differential pairs or the CPHY symbols.