Shift register, method for driving the same, gate driving circuit, and display device

A shift register comprising:

• a pull-up control circuit;
• a pull-up circuit;
• a pull-down control circuit;
• a pull-down circuit;
• a reset circuit;
• and
• a noise reduction control circuit,
• wherein the pull-up control circuit is connected between a signal input terminal and a pull-up node, and is configured to output a voltage of the signal input terminal to the pull-up node based on the signal input terminal,
• wherein the pull-up circuit is connected to the pull-up node, a first clock signal input terminal and a signal output terminal, and is configured to store a potential of the pull-up node and is configured to output a voltage of the first clock signal input terminal to the signal output terminal based on the pull-up node,
• wherein the pull-down control circuit is connected to a second clock signal input terminal, the pull-up node, a pull-down node and a first voltage terminal, and is configured to output a voltage of the second clock signal input terminal to the pull-down node based on the second clock signal input terminal, or configured to pull down a voltage of the pull-down node to a voltage of the first voltage terminal based on the pull-up node,
• wherein the pull-down circuit is connected to the pull-down node, the pull-up node, the signal output terminal and the first voltage terminal, and is configured to pull down a voltage of the pull-up node and a voltage of the signal output terminal to the voltage of the first voltage terminal based on the pull-down node,
• wherein the reset circuit is connected to a reset signal terminal, the pull-up node, the signal output terminal and the first voltage terminal, and is configured to pull down the voltage of the pull-up node and the voltage of the signal output terminal to the voltage of the first voltage terminal based on the reset signal terminal, and the reset circuit comprises a first transistor and a second transistor, a gate of the first transistor is connected to the reset signal terminal, a first pole of the first transistor is connected to the pull-up node, a second pole of the first transistor is connected to the first voltage terminal, and a gate of the second transistor is connected to the reset signal terminal, a first pole of the second transistor is connected to the signal output terminal, and a second pole of the second transistor is connected to the first voltage terminal,
• wherein the noise reduction control circuit is connected to a noise reduction control signal terminal and the pull-down node, and is configured to output a voltage of the noise reduction control signal terminal to the pull-down node based on the noise reduction control signal terminal in a blanking time of an image frame, and the noise reduction control circuit comprises a third transistor, a gate and a first pole of the third transistor are connected to the noise reduction control signal terminal, and a second pole of the third transistor is connected to the pull-down node, and
• wherein the noise reduction control circuit is configured to, when the reset circuit makes the first transistor and the second transistor change from a conductive state to a cut-off state, make the third transistor change from a cut-off state to a conductive state.