Display device

A display device, comprising:

• a plurality of shift register groups, configured to receive a first clock group and a second clock group having a first frequency and a second frequency, respectively, and the first frequency is higher than the second frequency;
• a plurality of multiplexer groups;
• a driver IC, configured to control the plurality of shift register groups and the plurality of multiplexer groups;
• a plurality of pixel circuits, arranged as a pixel array comprising rows of pixel circuits and columns of pixel circuits, wherein a shift register group of the plurality of shift register groups and a multiplexer group of the plurality of multiplexer groups cooperatively drive a part of pixel circuits of the plurality of pixel circuits;
• a plurality of switching circuits, correspondingly coupled with the plurality of multiplexer groups, wherein each of the plurality of switching circuits is configured to receive, from the driver IC, a switching signal of a plurality of switching signals and a plurality of multiplexing signals, when the switching signal of the plurality of switching signals has a first voltage level, the switching circuit outputs the plurality of multiplexing signals to one of the plurality of multiplexer groups coupled with the switching circuit to enable the one of the plurality of multiplexer groups, and when the switching signal has a second voltage level, the switching circuit is disabled from outputting the plurality of multiplexing signals;
• and
• a plurality of internal signal lines, extended from a peripheral area into an active area of the display device, and configured to transmit the plurality of switching signals to the plurality of pixel circuits,
• wherein when the shift register group of the plurality of shift register groups and the multiplexer group of the plurality of multiplexer groups are enabled in a first time period and the shift register group of the plurality of shift register groups is configured to operate according to the first frequency, other shift register groups of the plurality of shift register groups and other multiplexer groups of the plurality of multiplexer groups are enabled in a second time period within the first time period and the other shift register groups of the plurality of shift register groups are configured to operate according to the second frequency, in which one of the plurality of switching signals received by the part of pixel circuits is maintained at the first voltage level during the first time period,
• wherein another of the plurality of switching signals received by the another part of pixel circuits is maintained at the first voltage level during the second time period, and is maintained at the second voltage level during a third time period, in which a length of the first time period is equal to a sum of a length of the second time period and a length of the third time period,
• wherein the first time period is longer than the second time period so that the part of pixel circuits and the another part of pixel circuits have a first frame rate and a second frame rate, respectively, and the first frame rate is higher than the second frame rate,
• wherein the plurality of pixel circuits is arranged in the active area, and the plurality of shift register groups, the plurality of multiplexer groups, the driver IC, and the plurality of switching circuits are disposed in the peripheral area.