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US 10,950,155 B1Granted
GOA circuit and display panel
AssigneeShenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
InventorYan Xue
Life of this patent
Estimating the term…
Abstract
A GOA circuit and a display panel are provided. The GOA circuit could reduce the number of transistors electrically connected to the first node in the GOA circuit. Thus, the number of the current leakage paths is also reduced. In addition, the GOA circuit could real-time compensate the pixel circuit in the blank time period and thus raise the stability of the GOA circuit.
Claims18
A gate driver on array (GOA) circuit, comprising:
- a plurality of GOA circuits connected in series, each of the GOA circuits comprises a pull-up control module, a pull-down control module, a pull-up module, a first pull-down module, a second pull-down module, a first pull-down maintaining module, a second pull-down maintaining module, a logical addressing module and an inverter module;
- wherein the pull-up control module receives a stage signal of a previous stage and is electrically connected to a first node and a fourth node, and the pull-up control module is configured to output the stage signal of the previous stage to the first node under control of the stage signal and a voltage level of the fourth node;
- wherein the pull-up module receives a first clock signal, a second clock signal and a third clock signal and is electrically connected to the first node, a fifth node, a sixth node and a seventh node, and the pull-up module is configured to output a stage signal of a current stage, a first scan signal of the current stage and a second scan signal of the current stage under control of a voltage level of the first node;
- wherein the first pull-down module receives a stage signal of a next stage and a first low reference signal and is electrically connected to the first node and the fourth node, and the first pull-down module is configured to pull-down the voltage level of the first node according to the voltage level of the fourth node, the stage signal of the next stage and the first low reference signal;
- wherein the second pull-down module receives the stage signal of the previous stage, a reset signal and a second low reference signal and is electrically connected to a second node and a third node, the second pull-down module is configured to pull down a voltage level of the second node according to the reset signal, the second low reference signal and a voltage level of the third node;
- wherein the first pull-down maintaining module receives the first low reference signal and is electrically connected to the first node, the second node and the fourth node, the first pull-down maintaining module is configured to maintain the voltage level of the first node according to the first low reference signal, a voltage of the second node and a voltage of the fourth node after the first pull-down module pulls down the voltage level of the first node;
- wherein the second pull-down maintaining module receives the first low reference signal and a third low reference signal and is electrically connected to the second node, the fifth node, the sixth node and the seventh node, and the second pull-down maintaining module is configured to maintain voltage levels of the stage signal of the current stage, the first scan signal of the current stage and the second scan signal of the current stage according to the first low reference signal, the third low reference signal and the voltage of the second node;
- wherein the logical addressing module receives the stage signal of the previous stage, a high reference signal, the first low reference signal, the reset signal, a first control signal, and a second control signal and is electrically connected to the first node and the second node, and the logical addressing module is configured to control the voltage level of the first node according to the stage signal of the previous stage, the high reference signal, the reset signal, the first control signal and the voltage level of the second node in a blank time period;
- and
- wherein the inverter module receives the second low reference signal and the high reference signal and is electrically connected to the first node and the second node and the inverter module is configured to keep the voltage level of the second node has an inverting phase of the voltage level of the first node.
7 more elements
A display panel comprising a gate driver on array (GOA) circuit, the GOA circuit comprising:
- a plurality of GOA circuits connected in series, each of the GOA circuits comprises a pull-up control module, a pull-down control module, a pull-up module, a first pull-down module, a second pull-down module, a first pull-down maintaining module, a second pull-down maintaining module, a logical addressing module and an inverter module;
- wherein the pull-up control module receives a stage signal of a previous stage and is electrically connected to a first node and a fourth node, and the pull-up control module is configured to output the stage signal of the previous stage to the first node under control of the stage signal and a voltage level of the fourth node;
- wherein the pull-up module receives a first clock signal, a second clock signal and a third clock signal and is electrically connected to the first node, a fifth node, a sixth node and a seventh node, and the pull-up module is configured to output a stage signal of a current stage, a first scan signal of the current stage and a second scan signal of the current stage under control of a voltage level of the first node;
- wherein the first pull-down module receives a stage signal of a next stage and a first low reference signal and is electrically connected to the first node and the fourth node, and the first pull-down module is configured to pull-down the voltage level of the first node according to the voltage level of the fourth node, the stage signal of the next stage and the first low reference signal;
- wherein the second pull-down module receives the stage signal of the previous stage, a reset signal and a second low reference signal and is electrically connected to a second node and a third node, the second pull-down module is configured to pull down a voltage level of the second node according to the reset signal, the second low reference signal and a voltage level of the third node;
- wherein the first pull-down maintaining module receives the first low reference signal and is electrically connected to the first node, the second node and the fourth node, the first pull-down maintaining module is configured to maintain the voltage level of the first node according to the first low reference signal, a voltage of the second node and a voltage of the fourth node after the first pull-down module pulls down the voltage level of the first node;
- wherein the second pull-down maintaining module receives the first low reference signal and a third low reference signal and is electrically connected to the second node, the fifth node, the sixth node and the seventh node, and the second pull-down maintaining module is configured to maintain voltage levels of the stage signal of the current stage, the first scan signal of the current stage and the second scan signal of the current stage according to the first low reference signal, the third low reference signal and the voltage of the second node;
- wherein the logical addressing module receives the stage signal of the previous stage, a high reference signal, the first low reference signal, the reset signal, a first control signal, and a second control signal and is electrically connected to the first node and the second node, and the logical addressing module is configured to control the voltage level of the first node according to the stage signal of the previous stage, the high reference signal, the reset signal, the first control signal and the voltage level of the second node in a blank time period;
- and
- wherein the inverter module receives the second low reference signal and the high reference signal and is electrically connected to the first node and the second node and the inverter module is configured to keep the voltage level of the second node has an inverting phase of the voltage level of the first node.
7 more elements
Dependencies are inferred from the claim text.