Coarse grain coherency
AssigneeIntel Corporation
InventorsJoydeep Ray, Altug Koker, James A. Valerio, David Puffer, Abhishek R. Appu, Stephen Junkins
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Abstract
One embodiment provides for a general-purpose graphics processing device comprising a general-purpose graphics processing compute block to process a workload including graphics or compute operations, a first cache memory, and a coherency module enable the first cache memory to coherently cache data for the workload, the data stored in memory within a virtual address space, wherein the virtual address space shared with a separate general-purpose processor including a second cache memory that is coherent with the first cache memory.
Claims20
An electronic device comprising:
- a general-purpose processor including a first cache memory and a first coherency module;
- and
- a general-purpose graphics processor including a second cache memory and a second coherency module, wherein the first coherency module and the second coherency module enable heterogeneous coherency between the first cache memory and the second cache memory, the heterogeneous coherency enabled at multiple cache line granularity;
- and
- one or more memory controllers coupled with the general-purpose processor and the general-purpose graphics processor, the one or more memory controllers to enable communication with a memory module to store a superline directory table, wherein the superline directory table is to track ownership for a superline owned by the general-purpose processor and the general-purpose graphics processor, wherein the superline is a sub-page address region that spans multiple cache lines of the first cache memory and the second cache memory.
A data processing system comprising:
- a general-purpose processor including a first cache memory and a first coherency module;
- a system bus coupled with the general-purpose processor;
- and
- a general-purpose graphics processor coupled with general-purpose processor via the system bus, the general-purpose graphics processor including a second cache memory and a second coherency module, wherein the first coherency module and the second coherency module enable heterogeneous coherency between the first cache memory and the second cache memory, the heterogeneous coherency enabled at multiple cache line granularity;
- and
- a memory module to store a superline directory table, wherein the superline directory table is to track ownership for a superline owned by the general-purpose processor and the general-purpose graphics processor, wherein the superline is a sub-page address region that spans multiple cache lines of the first cache memory and the second cache memory.
Dependencies are inferred from the claim text.