Flexible neural network accelerator and methods therefor

A computer-implemented system, comprising:

• at least one internal buffer to hold layer data associated with at least one layer to be processed;
• and
• a plurality of fixed function logic blocks that are logically parallel so that multiple ones of the logic blocks have substantially the same arrangement of logic elements to compute a value associated with the layer of the neural network and by receiving the layer data of the at least one internal buffer, wherein the internal buffer is disposed locally to the fixed function logic blocks,
• wherein the logic blocks cooperatively form a multiplication portion of a multiplication-addition circuit (MAC) so that each logic block provides a weighted input to a same accumulator portion of the MAC, and
• wherein parallel logic elements of multiple logic blocks of the plurality of logic blocks are to provide the option to alternatively use weights of at least two different bit lengths comprising weights of a first bit length as inputted to the logic block and weights of a second bit length as inputted to the logic block, and to apply a scale factor to weights provided in at least the first bit length, and to omit the scale factor when weights are provided in at least the second bit length, and wherein the parallel logic elements of an individual logic block comprise multiple weight branches to receive weight input wherein each branch handles weights of a different bit length than the bit length of the other branches.

A computer implemented method of neural network propagation, comprising:

• computing a value of a layer of a neural network by using a plurality of fixed function hardware logic blocks that are substantially logically parallel so that multiple ones of the logic blocks have substantially the same arrangement of logic elements, wherein the logic blocks cooperatively form a multiplication portion of a multiplication-addition circuit (MAC) so that each logic block provides a weighted input to a same accumulator portion of the MAC;
• inputting a weight having a bit length from at least two alternative bit lengths available to input weights to the plurality of logic blocks wherein the available bit lengths comprise at least a first bit length and a second bit length, and wherein the logic elements of an individual logic block comprise multiple weight branches to receive weight input wherein each branch handles weights of a different bit length than the bit length of the other branches;
• and
• applying a scale factor by the logic blocks to weights provided in at least the first bit length, and to omit the scale factor when weights are provided in at least the second bit length.