System for designing a semiconductor device, device made, and method of using the system

A system for manufacturing a semiconductor device comprising:

• a design rule checking tool configured to determine whether a layout design of the semiconductor device satisfies at least one design rule, the layout design including a plurality of active cells;
• a layout style determination tool configured to detect whether the plurality of active cells of the semiconductor device have a distributed layout style that a plurality of electrically coupled gate electrode fingers are distributed in a first cell and a second cell, the first cell being on an edge of a cell array, the second cell being adjacent to the first cell and away from the edge of the cell array;
• and
• a dummy insertion tool configured to revise the layout design of the semiconductor device by performing dummy insertion of the layout design based on at least information from the layout style determination tool or the design rule checking tool, the performing dummy insertion includes inserting at least one dummy cell between the plurality of active cells and an outside edge of the semiconductor device, the dummy cell being part of a buffer zone outside of the cell array, wherein at least one of the above tools is configured for the semiconductor device to be fabricated based on at least the layout design.

A system for manufacturing a semiconductor device comprising:

• a layout style determination tool configured to detect whether a plurality of cells of a layout design of the semiconductor device including a first cell and a second cell have a distributed layout style that a plurality of electrically coupled gate electrode fingers are distributed in the first cell and the second cell, the first cell being on an edge of a cell array, and the second cell being adjacent to the first cell and away from the edge of the cell array;
• an array edge detection tool configured to determine whether the layout design of the semiconductor device comprises a buffer zone outside of the cell array, the buffer zone comprising one or more dummy cells;
• a design rule check tool configured to determine whether the layout design satisfies at least one design rule, the design rule check tool being configured to perform a design rule check on the layout design;
• and
• a dummy insertion tool configured to revise the layout design of the semiconductor device by performing dummy insertion of the layout design based on information from the layout style determination tool and the design rule check tool, wherein at least one of the above tools is configured for the semiconductor device to be fabricated based on at least the layout design.