Model order reduction in transistor level timing

A method comprising:

• reducing resistive and capacitive elements of a network into a representation of a loading network which has a reduced-order of terms, wherein the reduced-order of terms is a Pi (π) model;
• running simulations with perturbed parameters of the loading network;
• computing a derivative of parameters of the Pi model to loading network parasitics analytically by exploiting Sherman-Morrison rank one update formula;
• fabricating a chip including a circuit having the loading network parasitics;
• analytically calculating derivatives of reduced-order model parameters of the loading network with respect to each resistance (R) and capacitance (C);
• and
• from conductance and capacitance matrices of the loading network, computing first three moments of input admittance, from which each of the Pi model parameters can be calculated.

A method comprising:

• reducing resistive and capacitive elements of a network into a representation of a loading network which has a reduced-order of terms, wherein the reduced-order of terms is a Pi (π) model;
• running simulations with perturbed parameters of the loading network;
• computing a derivative of parameters of the Pi model to loading network parasitics analytically by exploiting Sherman-Morrison rank one update formula;
• fabricating a chip including a circuit having the loading network parasitics;
• and finding a finite difference of timing quantities using the simulations and a baseline simulation with no perturbations.