Co-simulation execution platform
AssigneeHitachi Automotive Systems, Ltd.
InventorIchiki Homma
Life of this patent
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Abstract
Example implementations described herein are directed to resolving issues related to the processor model in the S-PILS (Simulated Processor In the Loop Simulation) system, such as processor model correctness and simulation execution speed, by using the actual Central Processing Unit (CPU) board with silicon CPU instead of the virtual SoC model in the S-PILS.
Claims12
A co-simulation platform system, comprising:
- a central processing unit (CPU) board comprising:
- a memory configured to store firmware;
- a CPU configured to execute the firmware;
- and
- a timer configured to calculate event occurrence timing during execution of the firmware;
- and
- a host computer connected to the CPU board via an interface (I/F), the host computer comprising:
- a processor configured to execute a virtual plant model on a simulation engine;
- wherein the firmware is configured to control the virtual plant model;
- wherein the processor and the CPU are configured to synchronize with the event occurrence timing calculated by the timer to execute co-simulation between the virtual plant model and the firmware;
- wherein the processor and the CPU are configured to synchronize with the event occurrence timing calculated by the timer to execute co-simulation between the virtual plant model and the firmware by:
- execution of the firmware by the CPU until the event occurrence timing is reached;
- transmission of the event occurrence timing from the CPU board to the host computer via the I/F to control the virtual plant model to execute;
- execution of the virtual plant model on the simulation engine by the processor until the event occurrence timing is reached;
- synchronization of the virtual plant model with the firmware;
- and
- calculation of a next event occurrence timing by the timer.
A host computer connected, via an interface (I/F) to a central processing unit (CPU) board comprising a memory configured to store firmware, a CPU configured to execute the firmware, and a timer configured to calculate event occurrence timing during execution of the firmware, the host computer comprising:
- a processor configured to execute a virtual plant model on a simulation engine;
- wherein the firmware is configured to control the virtual plant model;
- wherein the processor and the CPU are configured to synchronize with the event occurrence timing calculated by the timer to execute co-simulation between the virtual plant model and the firmware;
- wherein the processor and the CPU are configured to synchronize with the event occurrence timing calculated by the timer to execute co-simulation between the virtual plant model and the firmware by:
- execution of the firmware by the CPU until the event occurrence timing is reached;
- transmission of the event occurrence timing from the CPU board to the host computer via the I/F to control the virtual plant model to execute;
- execution of the virtual plant model on the simulation engine by the processor until the event occurrence timing is reached;
- synchronization of the virtual plant model with the firmware;
- and
- calculation of a next event occurrence timing by the timer.
Dependencies are inferred from the claim text.