Hardware based state signature generation and check for test and debug of semiconductor circuit functionality

A method of detecting a functional fault in a circuit design undergoing hardware emulation, the method comprising:

• transferring register values of a corresponding reference circuit design to a hardware emulation system performing the hardware emulation;
• comparing, in each cycle of K of a clock and at the hardware emulation system, cycle K register values of the corresponding reference circuit with the cycle K register values of the circuit design undergoing emulation, wherein K is an integer ranging from 1 to N and N is an integer greater than one;
• and
• detecting, in each cycle K of the clock and at the hardware emulation system, whether a mismatch exists between the cycle K reference circuit design register values and the cycle K register values of the circuit design undergoing emulation.

A method of detecting a functional fault in a circuit design undergoing hardware emulation, the method comprising:

• computing N signatures of a corresponding reference circuit design during each of N clock cycles, N being an integer greater than one;
• computing N signatures of the circuit design undergoing emulation during each of the N clock cycles;
• comparing, for each of the N clock cycles, the signature of the reference circuit design to the signature of the circuit design undergoing emulation;
• and
• detecting, during each of the N clock cycles, whether a mismatch exists between the reference circuit design signature and the signature of the circuit design undergoing emulation, wherein each signature is computed by performing a logic function on a plurality of values of registers and flip-flops disposed in the circuit design.

A hardware emulation circuit configured to emulate a circuit design, the hardware emulation circuit being further configured to:

• receive N signatures of a corresponding reference circuit design during each of N clock cycles, N being an integer greater than one;
• compute N signatures of the circuit design undergoing emulation during each of the N clock cycles;
• compare, for each of the N clock cycles, the signature of the reference circuit design to the signature of the circuit design undergoing emulation;
• and
• detect, during each of the N clock cycles, whether a mismatch exists between the reference circuit design signature and the signature of the circuit design undergoing emulation, wherein each signature is computed by performing a logic function on a plurality of values of registers and flip-flops disposed in the circuit design.