Control path verification of hardware design for pipelined process
AssigneeImagination Technologies Limited
InventorsAshish Darbari, Sam Elliott
Life of this patent
Estimating the term…
Abstract
Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.
Claims20
A method to determine whether logic for implementing a pipelined process in hardware correctly moves data through the pipelined process, the method comprising:
- (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process;
- (b) in response to determining that the watched data has been input to the pipelined process, counting a number of progressing clock cycles for the watched data;
- (c) monitoring data output from the pipelined process to determine when the watched data has been output from the pipelined process;
- and
- (d) in response to determining that the watched data has been output from the pipelined process, determining whether the logic for implementing the pipelined process in hardware correctly moves data through the pipelined process, by comparing the counted number of progressing clock cycles for the watched data to one or more predetermined values.
A pipeline control path verification system to determine whether logic for implementing a pipelined process in hardware correctly moves data through the pipelined process, the system comprising:
- input logic configured to monitor data input to the pipelined process to determine when watched data has been input to the pipelined process;
- clock cycle tracking logic configured to, in response to the input logic determining that the watched data has been input to the pipelined process, count a number of progressing clock cycles for the watched data;
- output logic configured to monitor data output from the pipelined process to determine when the watched data has been output from the pipelined process;
- and
- logic configured to, in response to the output logic determining that the watched data has been output from the pipelined process, determine whether the logic for implementing the pipelined process in hardware correctly moves data through the pipelined process, by comparing the counted number of progressing clock cycles for the watched data to one or more predetermined values.
Dependencies are inferred from the claim text.