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US 10,949,571 B2Granted
Method and system for preventing unauthorized processor mode switches
AssigneeTexas Instruments Incorporated
InventorGregory R. Conti
Life of this patent
Estimating the term…
Abstract
Disclosed embodiments relate to a system having a processor adapted to activate multiple security levels for the system and a monitoring device coupled to the processor and employing security rules pertaining to the multiple security levels. The monitoring device restricts usage of the system if the processor activates the security levels in a sequence contrary to the security rules.
Claims12
A system comprising:
- a processor operable in one of a plurality of modes, the plurality of modes including a first secure mode, a second secure mode, a first non-secure mode, a second non-secure mode, and an intermediate mode between the first secure mode and the first non-secure mode;
- a register comprising a security bit, wherein a value of the security bit determines whether the processor is operating in the first secure mode, the second secure mode, the first non-secure mode, or the second non-secure mode;
- and
- monitoring logic operable to cause the system to perform a protective action in response to determining an occurrence of a security violation, the security violation being a determination that the processor attempts to switch from operating in the second non-secure mode to operating in either one of the intermediate mode, the first secure mode, or the second secure mode without transitioning to the first non-secure mode.
1 more element
A system comprising:
- a processor operable in one of a plurality of operating modes, the plurality of modes including a secure mode, a non-secure mode, and an intermediate mode between the secure mode and the non-secure mode;
- a register comprising a security bit, wherein a value of the security bit determines whether an operating mode is the secure mode or in the non-secure mode, wherein adjustment of the value of the security bit is permitted only in the intermediate mode;
- memory including a non-secure portion to store data;
- and
- monitoring logic operable to cause the system to perform a protective action in response to determining an occurrence of a security violation, the security violation being a determination that the processor attempts to read data from or write data to the non-secure portion of the memory while in the intermediate mode.
2 more elements
Dependencies are inferred from the claim text.