Data processor using a ring bus and method for controlling the same

A data processor, comprising:

• a plurality of relay circuits;
• a plurality of bus masters;
• a plurality of slaves which are accessed from the bus masters, each of the slaves which is coupled to an associated one of relay circuits;
• and
• a ring bus through which the relay circuits are coupled in the shape of a ring;
• wherein each of the relay circuits includes:
• an arbitration circuit which receives an adjacent response packet from an adjacent relay circuit and a slave response packet from the associated one of the slaves, and arbitrates the adjacent response packet and the slave response packet based on priority of the adjacent response packet and priority of the slave response packet to output one of the adjacent response packet and the slave response packet to a next relay circuit based on an arbitration result,
• a priority adjustment circuit which has a table in which the predetermined threshold value based on the number of the relay circuits through which the slave response packet passes before reaching its destination is stored, and adjusts the priority of the slave response packet based on the predetermined threshold value corresponding the destination of the slave response packet according to arbitration result.