Multiprocessor software-defined solid-state storage drive

A solid state storage device comprising:

• a plurality of protected flash memory modules each having a plurality of flash memory devices, a flash memory controller, power protection circuitry and interconnect interface;
• a socketed interconnect into which each of the protected flash memory modules is removably inserted;
• a host interface;
• a program code store;
• a multicore flash processor coupled to each of the protected flash memory modules via the socketed interconnect and to the host interface such that the multicore flash processor is disposed between each of the protected flash memory modules and the host interface, and wherein the multicore flash processor executes program code stored in the program code store such that an external agent interacting with the solid state storage device via the host interface perceives the solid state storage device as a single flash storage device instead of multiple flash storage devices with flash controllers disposed respectively on the protected flash memory modules;
• an enclosure having a fixed exterior dimension that conforms to an industry-standard form factor and wherein the socketed interconnect is disposed within the enclosure and enables storage capacity of the solid state storage device to be decreased by removing one or more of the protected flash memory modules or increased by inserting, within the enclosure, one or more additional protected flash memory modules;
• and
• wherein wear-leveling is performed in two stages including a first stage implemented by the multicore flash processor through selective distribution of write operations to the protected flash memory modules and a second stage implemented by the flash memory controller within each of the protected flash memory modules, wherein the flash memory controller within each one of the protected flash memory modules implements the second stage of wear-leveling by distributing write operations to the flash memory devices without buffering of write operations outside the one of the protected flash memory modules and without error code correction (ECC) outside the one of the protected flash memory modules such that buffering of write operations and error code correction is distributed among the plurality of protected flash memory modules.