Storage device and cache area addressing method

A storage device, comprising:

• a memory module;
• a buffer, comprising a cache area and a plurality of banks, wherein the cache area is arranged in one of the banks;
• a memory controller coupled to the memory module and the buffer, comprising a logical address arrangement, wherein the logical arrangement comprises a logical address interval corresponding to the cache area and a first logical address interval, the logical address interval is free of overlapping with the first logical address interval, and a size of the first logical address interval is equivalent to a size of each of the banks;
• and
• a cache area addressing circuit coupled to the memory controller and the buffer, and configured to perform:
• receiving a logical address from the memory controller;
• determining whether the logical address corresponds to the logical address interval corresponding to the cache area;
• when the logical address corresponds to the logical address interval corresponding to the cache area, mapping the logical address to a first physical address in the cache area according to a base address;
• and
• when the logical address does not correspond to the logical address interval corresponding to the cache area, mapping the logical address to a second physical address in the buffer.