Multiple data channel memory module architecture

An apparatus comprising:

• a processor configured to provide memory commands for memory access operations;
• and
• a memory controller coupled to the processor;
• and
• a memory comprising:
• a plurality of memory elements;
• and
• control logic coupled to the memory controller via a control channel, the control logic is further configured to select an internal control channel of a plurality of internal control channels based on decoded control information, wherein each internal control channel provides at least a portion of the decoded control information, independently of the other internal control channel of the plurality of internal control channels, to a respective memory element of the plurality of memory elements.

An apparatus comprising:

• a processor comprising an instruction set including a memory access request;
• a memory controller coupled to the processor and configured to receive the memory access request and to provide address/control information responsive to the memory access request;
• and
• a memory comprising a plurality of memory elements and control logic, wherein the control logic is coupled to the memory controller via an external address/control channel, the control logic configured to receive and decode the address/control information and to provide the decoded address/control information to at least one of the plurality of memory elements to control data transfer over multiple data channels, wherein each memory element is coupled to the control logic via a respective internal address/control channel of a plurality of internal address/control channels, wherein each internal address/control channel provides respective decoded internal address/control information, independently of the other internal address/control channels.