Data flush of a persistent memory cache or buffer

A memory controller for a data processing system including a plurality of processing units, an interconnect fabric, and a system memory coupled to the memory controller, the system memory including a persistent memory device and a non-persistent cache interposed between the memory controller and the persistent memory device, wherein the memory controller comprises integrated circuitry configured to perform:

• the memory controller controlling read and write access to the system memory based on memory access requests received from the plurality of processing units on the interconnect fabric, wherein the controlling includes:
• receiving on the interconnect fabric a flush request of a particular processing unit among the plurality of processing units that initiated the flush request, the flush request specifying a target address;
• and
• the memory controller, based on receipt of the flush request, ensuring flushing of a target cache line of data identified by target address from the non-persistent cache into the persistent memory device, wherein the ensuring flushing includes the memory controller, based on receipt of a coherence message indicating that the memory controller is an only snooping coherence participant in the data processing system processing the flush request and based on completion of a pending local write request to the target cache, issuing a flush command to the non-persistent cache that initiates flushing of the target cache into the persistent memory device.

A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a memory controller for a data processing system including a plurality of processing units, an interconnect fabric, and a system memory coupled to the memory controller, the system memory including a persistent memory device and a non-persistent cache interposed between the memory controller and the persistent memory device, wherein the memory controller comprises integrated circuitry configured to perform:
• the memory controller controlling read and write access to the system memory based on memory access requests received from the plurality of processing units on the interconnect fabric, wherein the controlling includes:
• receiving on the interconnect fabric a flush request of a particular processing unit among the plurality of processing units that initiated the flush request, the flush request specifying a target address;
• and
• the memory controller, based on receipt of the flush request, ensuring flushing of a target cache line of data identified by target address from the non-persistent cache into the persistent memory device, wherein the ensuring flushing includes the memory controller, based on receipt of a coherence message indicating that the memory controller is an only snooping coherence participant in the data processing system processing the flush request and based on completion of a pending local write request to the target cache, issuing a flush command to the non-persistent cache that initiates flushing of the target cache into the Persistent memory device.