Binary instrumentation to trace graphics processor code
AssigneeIntel Corporation
InventorKonstantin Levit-Gurevich
Life of this patent
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Abstract
An embodiment of a semiconductor package apparatus may include technology to determine a size for a trace buffer based on instrumented code to be executed on a graphics processor, initialize the trace buffer in a shared memory based on the determined size, provide the instrumented code to the graphics processor to be executed, collect data in the trace buffer from the executed instrumented code, analyze the data collected in the trace buffer on a processor, and generate a trace of the instrumented code on the processor based on the analyzed data. Other embodiments are disclosed and claimed.
Claims25
An electronic processing system, comprising:
- a host processor;
- a graphics processor;
- memory communicatively coupled to the host processor and the graphics processor;
- and
- logic communicatively coupled to the host processor and the graphics processor to:
- analyze, with the host processor, code that is to be instrumented to determine a size for a trace buffer based on types of memory instructions within each block of a plurality of blocks of the code,
- instrument, with the host processor, the code to generate instrumented code to be executed on the graphics processor,
- initialize, with the host processor, the trace buffer in the memory based on the determined size,
- provide the instrumented code to the graphics processor to be executed,
- collect data in the trace buffer from the executed instrumented code,
- bypass a storage of data from the executed instrumented code in the trace buffer in response to the trace buffer reaching a threshold amount,
- analyze the data collected in the trace buffer on the host processor, and
- generate a trace of the instrumented code on the host processor.
A semiconductor package apparatus for use with a graphics processor, comprising:
- one or more substrates;
- and
- logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic or fixed-functionality logic hardware, the logic coupled to the one or more substrates to:
- analyze, with a host processor, code that is to be instrumented to determine a size for a trace buffer based on types of memory instructions within each block of a plurality of blocks of the code,
- instrument, with the host processor, the code to generate instrumented code to be executed on a graphics processor,
- initialize, with the host processor, the trace buffer in a shared memory based on the determined size,
- provide the instrumented code to the graphics processor to be executed,
- collect data in the trace buffer from the executed instrumented code,
- bypass a storage of data from the executed instrumented code in the trace buffer in response to the trace buffer reaching a threshold amount,
- analyze the data collected in the trace buffer on the host processor, and
- generate a trace of the instrumented code on the host processor based on the analyzed data.
A method of tracing code, comprising:
- analyzing code, with a host processor, that is to be instrumented to determine a size for a trace buffer based on types of memory instructions within each block of a plurality of blocks of the code;
- instrumenting, with the host processor, the code to generate instrumented code to be executed on a graphics processor;
- initializing, with the host processor, the trace buffer in a shared memory based on the determined size;
- providing the instrumented code to the graphics processor to be executed;
- collecting data in the trace buffer from the executed instrumented code;
- bypassing a storage of data from the executed instrumented code in the trace buffer in response to the trace buffer reaching a threshold amount;
- analyzing the data collected in the trace buffer on the host processor;
- and
- generating a trace of the instrumented code on the host processor based on the analyzed data.
At least one non-transitory computer readable storage medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:
- analyze, with a host processor, code that is to be instrumented to determine a size for a trace buffer based on types of memory instructions within each block of a plurality of blocks of the code;
- instrument, with the host processor, the code to generate instrumented code to be executed on a graphics processor;
- initialize, with the host processor, the trace buffer in a shared memory based on the determined size;
- provide the instrumented code to the graphics processor to be executed;
- collect data in the trace buffer from the executed instrumented code;
- bypass a storage of data from the executed instrumented code in the trace buffer in response to the trace buffer reaching a threshold amount
- analyze the data collected in the trace buffer on the host processor;
- and
- generate a trace of the instrumented code on the host processor based on the analyzed data.
Dependencies are inferred from the claim text.