Error correction code event detection
AssigneeMicron Technology, Inc.
InventorsYihua Zhang, Paolo E. Mangalindan, Jianfei Lei, Andrew D. Proescholdt, Gerard A. Kreifels
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Abstract
Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.
Claims20
A method of operating an electronic memory apparatus, comprising:
- performing a read operation on a set of memory cells;
- detecting an error in data read from the set of memory cells based at least in part on an error correction code (ECC) operation performed on the data;
- changing a voltage of an output pin of the electronic memory apparatus from a first level to a second level based at least in part on detecting the error, the second level indicating the error;
- and
- changing the voltage of the output pin from the second level to the first level based at least in part on determining that a threshold amount of time has elapsed since the error was detected.
An electronic memory apparatus, comprising:
- a memory array comprising memory cells;
- an error correction code (ECC) circuit in electronic communication with the memory array;
- and
- a memory controller in electronic communication with the ECC circuit, the memory controller operable to cause the electronic memory apparatus to:
- perform a read operation on a set of the memory cells;
- detect an error in data read from the set of the memory cells based at least in part on an ECC operation performed on the data by the ECC circuit;
- change a voltage of an output pin of the electronic memory apparatus from a first level to a second level based at least in part on detecting the error, the second level indicating the error;
- and
- change the voltage of the output pin from the second level to the first level based at least in part on determining that a threshold amount of time has elapsed since the error was detected.
An electronic memory apparatus, comprising:
- a memory array comprising memory cells and operable to perform a read operation on a set of the memory cells;
- an error correction code (ECC) circuit coupled with the memory array and operable to detect an error in the data read from the set of the memory cells based at least in part on an ECC operation performed on the data;
- and
- circuitry coupled with the ECC circuit and operable to change a voltage of an output pin of the electronic memory apparatus from a first level to a second level based at least in part on detecting the error, the second level indicating the error, and change the voltage of the output pin from the second level to the first level based at least in part on determining that a threshold amount of time has elapsed since the error was detected.
Dependencies are inferred from the claim text.