NAND device mixed parity management
AssigneeMicron Technology, Inc.
InventorGiuseppe Cariello
Life of this patent
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Abstract
Devices and techniques for NAND device mixed parity management are described herein. A first portion of data that corresponds to a first data segment and a second data segment—respectively defined with respect to a structure of a NAND device—are received. A parity value using the first portion of data and the second portion of data is computed and then stored for error correction operations.
Claims24
A controller for NAND device mixed parity management, the controller comprising:
- volatile memory;
- and
- processing circuitry to:
- receive a first portion of data, the first portion of data corresponding to a first data segment defined with respect to a structure of the NAND device;
- receive a second portion of data, the second portion of data corresponding to a second data segment defined with respect to the structure of the NAND device, the second data segment different than the first segment;
- compute a parity value using the first portion of data and the second portion of data;
- store the parity value in the volatile memory;
- and
- decouple parity data for the first portion of data and the second portion of data from parity data derived from the parity value in response to a trigger.
A method for NAND device mixed parity management, the method comprising:
- receiving a first portion of data, the first portion of data corresponding to a first data segment defined with respect to a structure of the NAND device;
- receiving a second portion of data, the second portion of data corresponding to a second data segment defined with respect to the structure of the NAND device, the second data segment different than the first segment;
- computing a parity value using the first portion of data and the second portion of data;
- storing the parity value;
- and
- decoupling parity data for the first portion of data and the second portion of data from parity data derived from the parity value in response to a trigger.
A non-transitory machine readable medium including instructions for NAND device mixed parity management, the instructions, when executed by processing circuitry, cause the processing circuitry to perform operations comprising:
- receiving a first portion of data, the first portion of data corresponding to a first data segment defined with respect to a structure of a NAND device;
- receiving a second portion of data, the second portion of data corresponding to a second data segment defined with respect to the structure of the NAND device, the second data segment different than the first segment;
- computing a parity value using the first portion of data and the second portion of data;
- storing the parity value;
- and
- decoupling parity data for the first portion of data and the second portion of data from parity data derived from the parity value in response to a trigger.
Dependencies are inferred from the claim text.