On-die ECC with error counter and internal address generation

A memory controller, comprising:

• a hardware interface to receive data from multiple memory devices, wherein a memory device includes on-die error checking and correction (ECC) circuitry to perform internal ECC operations to check and correct errors for multiple rows of the memory device, where the ECC circuitry is to generate address information internally to address the multiple rows for the internal ECC operations, the ECC circuitry having a counter to accumulate an error count, the error count to be incremented in response to detection of an error in any of the multiple rows of the memory device, wherein the on-die ECC circuitry is to generate an error result to store in an error count register of the memory device as a difference between the accumulated error count and a non-zero error threshold, wherein the error threshold represents a preset number of errors to exclude from the error result;
• and
• system-level ECC circuitry to perform ECC operations for the multiple memory devices, the system-level ECC circuitry to perform error correction based on check bits provided by the memory controller to the multiple memory devices and error counts from the multiple memory devices.