Implementing dynamic SEU detection and correction method and circuit

A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

• a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing SEU parity detection and correction, said SEU parity detection and correction detecting and correcting unwanted state changes due to SEUs in a latch, said SEU parity detection and correction circuit comprising:
• a plurality of L1 L2 latches connected in a chain, each L1 L2 latch includes an L1 latch and an L2 latch with each L2 latch having a connected output monitored for a flip;
• an L2 detect circuit XOR tree includes a plurality of XOR inputs, each of the plurality of XOR inputs connected to a true output of each respective L2 latch in the chain;
• and
• an L2 clock (LCK) trigger circuit connected to an output of the L2 detect circuit XOR tree and shared across each of the plurality of L1 L2 latches for correcting bit flip errors;
• wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said SEU parity detection and correction circuit.

A method for implementing single event upset (SEU) parity detection and correction comprising:

• providing a SEU parity detection and correction circuit for detecting and correcting unwanted state changes due to SEUs in a latch;
• providing a plurality of L1 L2 latches connected in a chain, each L1 L2 latch includes an L1 latch and an L2 latch with each L2 latch having a connected output monitored for a flip;
• providing an L2 detect circuit XOR tree that includes a plurality of XOR inputs, each of the plurality of XOR inputs connected to a true output of each respective L2 latch in the chain;
• and
• providing an L2 clock (LCK) trigger circuit connected to an output of the L2 detect circuit XOR tree and shared across each of the plurality of L1 L2 latches for correcting bit flip errors.