Memory interface having data signal path and tag signal path

An apparatus comprising:

• means for issuing a request specifying a target address indicating an addressed location in a memory system;
• means for responding to the request issued by the means for issuing;
• and
• means for performing a tag error checking operation when the request issued by the means for issuing is a tag-error-checking request specifying an address tag, the tag error checking operation comprising determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request;
• in which:
• the means for issuing and the means for responding are configured to communicate via a memory interface having at least:
• at least one data signal path to exchange read data or write data between the means for issuing and the means for responding;
• and
• at least one tag signal path, provided in parallel with the at least one data signal path, to exchange address tags or allocation tags between the means for issuing and the means for responding.

A method comprising:

• issuing, by a requester, a request specifying a target address indicating an addressed location in a memory system;
• responding, by a completer, to the request issued by the requester, wherein the requester and the completer communicate via a memory interface, and the requester and completer exchange read data or write data via at least one data signal path of the memory interface;
• and
• when the request issued by the requester is a tag-error-checking request specifying an address tag:
• performing a tag error checking operation comprising determining whether the address tag matches an allocation tag stored in the memory system associated with a block of one or more addresses comprising the target address specified by the tag-error-checking request;
• and
• exchanging address tags or allocation tags between the requester and the completer via at least one tag signal path;
• provided in parallel with the at least one data signal path.