Validation of a symbol response memory

A system, comprising:

• a host processor configured to initiate transmission of data to be analyzed;
• a memory coupled to the host processor and configured to store the data to be analyzed;
• and
• a state machine engine coupled to the host processor and to the memory, wherein the state machine engine is configured to:
• receive the data to be analyzed from the memory;
• and
• transmit a result of an analysis of the data by the state machine engine to the host processor, wherein the state machine engine comprises:
• a plurality of configurable elements, wherein each configurable element of the plurality of configurable elements is configured to be programmed via configuration data and to selectively output a result as a portion of the result of the analysis;
• and
• an error detection engine (EDE) configured to validate an integrity of the configuration data.

A system, comprising:

• a host processor configured to initiate transmission of data to be analyzed;
• and
• a state machine engine coupled to the host processor and configured to receive the data to be analyzed, wherein the state machine engine comprises:
• a finite state machine lattice comprising:
• a plurality of blocks, each block of the plurality of blocks comprising:
• a plurality of rows, each row of the plurality of rows comprising:
• a plurality of configurable elements, wherein each configurable element of the plurality of configurable elements comprises a memory programmed with configuration data to selectively set a data state of the as one of a high state or a low state, wherein the data state is utilized in an analysis of at least a portion of the data stream;
• and
• an error detection engine (EDE) configured to at least partially validate an integrity of the configuration data by determining whether an initial cyclic redundancy check (CRC) value generated based on the configuration data at a first time differs from a subsequent CRC value generated at a second time.