Logical register recovery within a processor

A computer system for processing information, the computer system comprising:

• at least one computer processor for processing instructions, the processor comprising:
• one or more physical register files having a plurality of entries to store data;
• one or more logical registers having a plurality of entries to store data;
• one or more logical registers mappers configured to map the entries in the one or logical registers to the entries in the one or more physical register files;
• and
• a history buffer having a plurality of recovery ports associated with the mapper, and a plurality of entries for storing information associated with a processor instruction evicted from the logical register,
• wherein,
• the logical register is partitioned into a plurality of ranges of logical register entries;
• each recovery port in the history buffer is assigned and dedicated to one of the plurality of ranges of logical register entries, such that each range of logical register entries is assigned a different one or more dedicated recovery ports of the history buffer;
• and
• history buffer entries, in response to a flush recovery process, are directed to the assigned, different one or more dedicated recovery ports of the history buffer based upon a logical register entry associated with the history buffer entry.

A computer system for processing information, the computer system comprising:

• at least one computer processor for processing instructions, the processor comprising:
• a physical register file that includes a plurality of entries to store data associated with the processor instructions;
• a logical register having a plurality of logical register entries, the logical register configured to have a plurality of ranges of logical register entries;
• one or more logical register mappers for the mapping the logical register entries to entries in the physical register file, the one or more logical register mappers having a plurality or restore ports with at least one mapper assigned to each range of logical register entries;
• and
• a history buffer associated with the logical register mapper and having a plurality of entries for storing information evicted by a younger processor instruction, the history buffer having a plurality of recovery ports,
• wherein the processor is configured to:
• assign each recovery port in the history buffer to one of the plurality of ranges of the logical register entries such that each range of logical register entries is assigned a different one or more dedicated recovery ports in history buffer;
• assign each recovery port in the history buffer to at least one restore port in the logical register mapper;
• and
• direct one or more history buffer entries to the assigned one or more dedicated recovery ports based upon a logical entry associated with the history buffer entry.