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US 10,949,207 B2Granted
Processor core supporting a heterogeneous system instruction set architecture
AssigneeIntel Corporation
InventorsToby Opferman, Russell C. Arnold, Vedvyas Shanbhogue
Life of this patent
Estimating the term…
Abstract
Embodiments of processors, methods, and systems for a processor core supporting a heterogenous system instruction set architecture are described. In an embodiment, a processor includes an instruction decoder and an exception generation circuit. The exception generation circuit is to, in response to the instruction decoder receiving an unsupported instruction, generate an exception and report an instruction classification value of the unsupported instruction.
Claims17
A processor comprising:
- an instruction decoder;
- and
- an exception generation circuit to, in response to the instruction decoder receiving an unsupported instruction, generate an exception and report an instruction classification value of the unsupported instruction, wherein the instruction classification value is to indicate which of plurality of extensions to an instruction set architecture includes the unsupported instruction.
A method comprising:
- receiving, by a first processor in a system, a first instruction, the first processor having a first instruction set architecture;
- generating, by the first processor, an exception in response to determining that the first instruction is not in the first instruction set architecture;
- and
- reporting an instruction classification of the first instruction, wherein the instruction classification value is to indicate which of plurality of extensions to the first instruction set architecture includes the unsupported instruction.
1 more element
A system comprising:
- a first processor having a first instruction set architecture (ISA) including a first extension including a first instruction;
- a second processor having the first ISA not including the first extension, the second processor including:
- an instruction decoder;
- and
- an exception generation circuit to, in response to the instruction decoder receiving the instruction, generate an exception and report an instruction classification value of the instruction, wherein the instruction classification value is to indicate that the first extension includes the first instruction.
2 more elements
Dependencies are inferred from the claim text.