Implementation of execution compression of instructions in slice target register file mapper

A method of executing a move instruction in a computer system, the method comprising:

• determining, via a dispatch routing network, that at least one received instruction is a move instruction to move data from a source register to a destination register;
• broadcasting, via the dispatch routing network, the move instruction to an issue queue and a splice target file (STF) mapper;
• analyzing a shared bit included in the move instruction;
• determining whether the source register is shared with the destination register at the time the move instruction is dispatched based on the shared bit;
• and
• performing a first move operation in response to the shared bit indicating the source register of the move instruction is not shared with a destination register;
• and
• performing a different second move operation in response to the shared bit indicating the source register of the move instruction is shared with a destination register,
• wherein the first move operation is a zero-cycle move operation that includes:
• determining, via the STF mapper, the source register of the move instruction and a source STF tag of the source register;
• and
• copying, via the STF mapper, the source STF tag into the destination register.

A computer program product to control a computer system to perform a move instruction operation, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by an electronic computer processor to control the computer system to perform operations comprising:

• determining, via a dispatch routing network, that at least one received instruction is a move instruction to move data from a source register to a destination register;
• broadcasting, via the dispatch routing network, the move instruction to an issue queue and a splice target file (STF) mapper;
• analyzing a shared bit included in the move instruction;
• determining whether the source register is shared with the destination register at the time the move instruction is dispatched based on the shared bit;
• and
• performing a first move operation in response to the shared bit indicating the source register of the move instruction is not shared with a destination register;
• and
• performing a different second move operation in response to the shared bit indicating the source register of the move instruction is shared with a destination register,
• wherein the first move operation is a zero-cycle move operation that includes:
• determining, via the STF mapper, the source register of the move instruction and a source STF tag of the source register;
• and
• copying, via the STF mapper, the source STF tag into the destination register.