Microcontroller with configurable logic peripheral
AssigneeMicrochip Technology Incorporated
InventorRyan Foss
Life of this patent
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Abstract
A microcontroller has a central processing unit, memory, I/O ports and a plurality of peripheral units, wherein one of the peripheral units is a configurable logic cell. The configurable logic cell is formed by a look-up table formed by a plurality of memory cells receiving a predefined number of input address signals selectable from internal signals provided by the peripheral units and at least one external signal provided by at least one external pin and generating an output signal. The central processing unit is configured to directly provide input address signals for the look-up table.
Claims21
A microcontroller comprising a central processing unit, memory, I/O ports and a plurality of peripheral units, wherein one of the peripheral units is a configurable logic cell, wherein the configurable logic cell is formed by a look-up table formed by a plurality of memory cells receiving a predefined number of input address signals selectable from internal signals provided by the peripheral units and at least one external signal provided by at least one external pin and generating an output signal and wherein the central processing unit is configured to directly provide input address signals for the look-up table.
A method of operating a microcontroller comprising a central processing unit, memory, I/O ports and a plurality of peripheral units, wherein one of the peripheral units is a configurable logic cell, wherein the configurable logic cell is formed by a look-up table formed by a plurality of memory cells receiving a predefined number of input address signals and generating an output signal and wherein the central processing unit is configured to directly provide input address signals for the look-up table, the method comprising:
- configuring the look-up table by loading predefined data into memory cells of the look-up table;
- selecting address signals from internal signals provided by the peripheral units and external signals provided by at least one external pin;
- buffering the selected address signals in a register or latch.
Dependencies are inferred from the claim text.