Processor with accelerated lock instruction operation

A processor, comprising:

• a cache memory;
• an atomic grouping unit, operatively coupled to the cache memory, and operative to:
• identify which of a plurality of older store instructions relative to a current lock instruction are able to be locked;
• and
• lock the identified older store instructions as an atomic group with the current lock instruction;
• and
• probe processing logic operative to negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory.

A computer system, comprising:

• a processor;
• and
• a memory that stores instructions for execution by the processor;
• wherein the processor comprises:
• cache memory;
• an atomic grouping unit, operatively coupled to the cache memory, and operative to:
• identify which of a plurality of older store instructions relative to a current lock instruction are able to be locked;
• and
• lock the identified older store instructions as an atomic group with the current lock instruction;
• and
• probe processing logic operative to negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory.