Error bounded multiplication by invariant rationals
AssigneeImagination Technologies Limited
InventorTheo Alan Drane
Life of this patent
Estimating the term…
Abstract
A hardware logic representation of a circuit to implement an operation to perform multiplication by an invariant rational is generated by truncating an infinite single summation array (which is represented in a finite way). The truncation is performed by identifying a repeating section and then discarding all but a finite number of the repeating sections whilst still satisfying a defined error bound. To further reduce the size of the summation array, the binary representation of the invariant rational is converted into canonical signed digit notation prior to creating the finite representation of the infinite array.
Claims11
A hardware logic multiplier configured to multiply an input value by a predetermined invariant rational that satisfies a defined error bound, wherein the hardware logic multiplier is synthesized using a process comprising:
- truncating a binary expansion of the predetermined invariant rational;
- converting the truncated binary expansion into canonical signed digit notation and expanding the canonical signed digit representation into a finite representation of an infinite expansion;
- generating a truncated single summation array from the infinite expansion by discarding one or more repeating sections of the array based upon the defined error bound;
- and
- synthesizing a representation of the hardware logic multiplier from the truncated single summation array, wherein the representation comprises a computer-readable dataset description which is usable in an integrated circuit manufacturing system to fabricate said hardware logic multiplier.
A non-transitory computer readable storage medium having stored thereon a computer-readable dataset representation of a hardware logic multiplier configured to multiply an input value by a predetermined invariant rational that satisfies a defined error bound, wherein the representation is usable in an integrated circuit manufacturing system to fabricate a hardware logic multiplier and is generated by:
- truncating a binary expansion of the predetermined invariant rational;
- converting the truncated binary expansion into canonical signed digit notation and expanding the canonical signed digit representation into a finite representation of an infinite expansion;
- generating a truncated single summation array from the infinite expansion by discarding one or more repeating sections of the array based upon the defined error bound;
- and
- synthesizing the representation of the hardware logic multiplier from the truncated single summation array.
Dependencies are inferred from the claim text.